Ngo; Minh V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ngo; Minh V..The latest application filed is for "method for manufacturing a surface mount device".

Company Profile

0.25.11

Ngo; Minh V. - San Jose CA
Ngo; Minh V. - Fremont CA
Ngo; Minh V. - Union City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Insulated thermal cut-off device Grant 9,831,054 - Chen , et al. November 28, 2	2017-11-28
Method for manufacturing a surface mount device Grant 9,659,690 - Sepulveda , et al. May 23, 2	2017-05-23
Method for manufacturing a surface mount device Grant 9,646,744 - Sepulveda , et al. May 9, 2	2017-05-09
Method for Manufacturing a Surface Mount Device App 20160104559 - Sepulveda; Mario G. ; et al.	2016-04-14
Method for Manufacturing a Surface Mount Device App 20160105965 - Sepulveda; Mario G. ; et al.	2016-04-14
Insulated Thermal Cut-Off Device App 20150279596 - Chen; Jianhua ; et al.	2015-10-01
Tensile strained substrate Grant 7,701,019 - Ngo , et al. April 20, 2	2010-04-20
Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing Grant 7,118,967 - Ngo , et al. October 10, 2	2006-10-10
Tensile strained substrate App 20060138479 - Ngo; Minh V. ; et al.	2006-06-29
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing Grant 7,018,896 - Ngo , et al. March 28, 2	2006-03-28
Sidewall formation for high density polymer memory element array Grant 7,015,504 - Lyons , et al. March 21, 2	2006-03-21
Semiconductor with tensile strained substrate and method of making the same Grant 7,001,837 - Ngo , et al. February 21, 2	2006-02-21
Post CMP precursor treatment Grant 6,982,188 - Xie , et al. January 3, 2	2006-01-03
Method of decontaminating equipment Grant 6,951,220 - Arasnia , et al. October 4, 2	2005-10-04
Strained silicon MOSFET having reduced leakage and method of its formation Grant 6,924,182 - Xiang , et al. August 2, 2	2005-08-02
Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends Grant 6,893,929 - Xiang , et al. May 17, 2	2005-05-17
Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control Grant 6,894,342 - Hui , et al. May 17, 2	2005-05-17
Sidewall formation for high density polymer memory element array App 20050092983 - Lyons, Christopher F. ; et al.	2005-05-05
Selective epitaxy to improve silicidation Grant 6,878,592 - Besser , et al. April 12, 2	2005-04-12
Depletion to avoid cross contamination Grant 6,858,503 - Ngo , et al. February 22, 2	2005-02-22
Structure and method for preventing process-induced UV radiation damage in a memory cell Grant 6,833,581 - Hui , et al. December 21, 2	2004-12-21
Isolation trench fill process Grant 6,806,165 - Hopper , et al. October 19, 2	2004-10-19
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing App 20040191989 - Ngo, Minh V. ; et al.	2004-09-30
Nickel alloy for SMOS process silicidation Grant 6,797,614 - Paton , et al. September 28, 2	2004-09-28
Mosfets incorporating nickel germanosilicided gate and methods for their formation Grant 6,787,864 - Paton , et al. September 7, 2	2004-09-07
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL Grant 6,774,432 - Ngo , et al. August 10, 2	2004-08-10
Uv-blocking Layer For Reducing Uv-induced Charging Of Sonos Dual-bit Flash Memory Devices In Beol Processing App 20040151025 - Ngo, Minh V. ; et al.	2004-08-05
Semiconductor with tensile strained substrate and method of making the same App 20040142545 - Ngo, Minh V. ; et al.	2004-07-22
Structure and method for preventing UV radiation damage and increasing data retention in memory cells Grant 6,765,254 - Hui , et al. July 20, 2	2004-07-20
Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer Grant 6,730,576 - Wang , et al. May 4, 2	2004-05-04
Mosfets incorporating nickel germanosilicided gate and methods for their formation App 20040061191 - Paton, Eric N. ; et al.	2004-04-01
Process for forming fully silicided gates Grant 6,562,718 - Xiang , et al. May 13, 2	2003-05-13
HSQ processing for reduced dielectric constant Grant 5,888,911 - Ngo , et al. March 30, 1	1999-03-30
HSQ baking for reduced dielectric constant Grant 5,888,898 - Ngo , et al. March 30, 1	1999-03-30

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.