Ng; Hung Y.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ng; Hung Y..The latest application filed is for "formation of improved soi substrates using bulk semiconductor wafers".

Company Profile

0.13.13

Ng; Hung Y. - New Milford NJ US
Ng; Hung Y. - Brooklyn VA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Substantially L-shaped silicide for contact Grant 8,643,119 - Luo , et al. February 4, 2	2014-02-04
Formation of improved SOI substrates using bulk semiconductor wafers Grant 8,268,698 - Henson , et al. September 18, 2	2012-09-18
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers App 20110147885 - Henson; William K. ; et al.	2011-06-23
Formation of improved SOI substrates using bulk semiconductor wafers Grant 7,932,158 - Henson , et al. April 26, 2	2011-04-26
Dual stress memory technique method and related structure Grant 7,785,950 - Fang , et al. August 31, 2	2010-08-31
Strained semiconductor device and method of making same Grant 7,772,676 - Han , et al. August 10, 2	2010-08-10
Complementary Metal-oxide-semiconductor Device With Embedded Stressor App 20090242989 - CHAN; KEVIN K. ; et al.	2009-10-01
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers App 20090039461 - Henson; William K. ; et al.	2009-02-12
Substantially L-shaped Silicide For Contact And Related Method App 20080283934 - Luo; Zhijiong ; et al.	2008-11-20
Formation of improved SOI substrates using bulk semiconductor wafers Grant 7,452,784 - Henson , et al. November 18, 2	2008-11-18
Method of forming substantially L-shaped silicide contact for a semiconductor device Grant 7,442,619 - Luo , et al. October 28, 2	2008-10-28
Method And Structure To Use An Etch Resistant Liner On Transistor Gate Structure To Achieve High Device Performance App 20080036017 - Ng; Hung Y. ; et al.	2008-02-14
Strained semiconductor device and method of making same App 20070295989 - Han; Jin-Ping ; et al.	2007-12-27
Semiconductor Structure Including Isolation Region With Variable Linewidth And Method For Fabrication Therof App 20070293016 - Luo; Zhijiong ; et al.	2007-12-20
Structure to use an etch resistant liner on transistor gate structure to achieve high device performance Grant 7,307,323 - Ng , et al. December 11, 2	2007-12-11
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers App 20070275537 - Henson; William K. ; et al.	2007-11-29
Substantially L-shaped Silicide For Contact And Related Method App 20070267753 - Luo; Zhijiong ; et al.	2007-11-22
Dual Stress Memory Technique Method And Related Structure App 20070105299 - Fang; Sunfei ; et al.	2007-05-10
Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance App 20060145275 - Ng; Hung Y. ; et al.	2006-07-06
Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance Grant 7,064,027 - Ng , et al. June 20, 2	2006-06-20
Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance App 20050104095 - Ng, Hung Y. ; et al.	2005-05-19
Vapor phase etch trim structure with top etch blocking layer Grant 6,884,734 - Buehrer , et al. April 26, 2	2005-04-26
Vapor phase etch trim structure with top etch blocking layer App 20040198030 - Buehrer, Frederick W. ; et al.	2004-10-07
Selective nitride: oxide anisotropic etch process Grant 6,656,375 - Armacost , et al. December 2, 2	2003-12-02
Selective and anisotropic dry etching Grant 4,734,157 - Carbaugh , et al. March 29, 1	1988-03-29

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