New; Bernard J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for New; Bernard J..The latest application filed is for "semiconductor device with stacked power converter".

Company Profile

0.104.34

New; Bernard J. - Carmel Valley CA
New; Bernard J. - San Jose CA
New; Bernard J. - Los Gatos CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device with stacked power converter Grant 9,177,944 - New November 3, 2	2015-11-03
Multiplier circuit configurable for real or complex operation Grant 8,572,153 - New October 29, 2	2013-10-29
Programmable device with dynamic DSP architecture Grant 8,495,122 - Simkins , et al. July 23, 2	2013-07-23
Semiconductor assembly with integrated circuit and companion device Grant 8,399,983 - New March 19, 2	2013-03-19
Hybrid integrated circuit device Grant 8,293,547 - Karp , et al. October 23, 2	2012-10-23
Method and apparatus for communicating data between stacked integrated circuits Grant 8,296,578 - New October 23, 2	2012-10-23
Method and apparatus for inter-IC communication Grant 8,244,933 - New August 14, 2	2012-08-14
Semiconductor Device With Stacked Power Converter App 20120139103 - New; Bernard J.	2012-06-07
Integrated circuit with through-die via interface for die stacking and cross-track routing Grant 8,089,299 - Rahman , et al. January 3, 2	2012-01-03
Programmable device with contact via programming Grant 7,984,407 - New July 19, 2	2011-07-19
Secure exchange of IP cores Grant 7,971,072 - Donlin , et al. June 28, 2	2011-06-28
Hybrid Integrated Circuit Device App 20110147949 - Karp; James ; et al.	2011-06-23
Software model for a hybrid stacked field programmable gate array Grant 7,930,661 - Trimberger , et al. April 19, 2	2011-04-19
Formation of a hybrid integrated circuit device Grant 7,919,845 - Karp , et al. April 5, 2	2011-04-05
Digital signal processing element having an arithmetic logic unit Grant 7,882,165 - Simkins , et al. February 1, 2	2011-02-01
Digital signal processing circuit having an adder circuit with carry-outs Grant 7,870,182 - Thendean , et al. January 11, 2	2011-01-11
Digital signal processing block having a wide multiplexer Grant 7,865,542 - New , et al. January 4, 2	2011-01-04
Digital signal processing circuit having a pattern circuit for determining termination conditions Grant 7,860,915 - Vadi , et al. December 28, 2	2010-12-28
Digital signal processing circuit having a SIMD circuit Grant 7,853,634 - Simkins , et al. December 14, 2	2010-12-14
Architectural floorplan for a digital signal processing circuit Grant 7,853,632 - Ching , et al. December 14, 2	2010-12-14
Digital signal processing circuit having a pattern detector circuit for convergent rounding Grant 7,853,636 - New , et al. December 14, 2	2010-12-14
Digital signal processing circuit having a pattern detector circuit Grant 7,849,119 - Vadi , et al. December 7, 2	2010-12-07
Digital signal processing circuit having a pre-adder circuit Grant 7,844,653 - Simkins , et al. November 30, 2	2010-11-30
Digital signal processing circuit having input register blocks Grant 7,840,627 - Simkins , et al. November 23, 2	2010-11-23
Arithmetic logic unit circuit Grant 7,840,630 - Wong , et al. November 23, 2	2010-11-23
Method and apparatus for initializing an integrated circuit Grant 7,830,171 - New November 9, 2	2010-11-09
Method and system for secure exchange of IP cores Grant 7,788,502 - Donlin , et al. August 31, 2	2010-08-31
Apparatus for interconnecting stacked dice on a programmable integrated circuit Grant 7,619,441 - Rahman , et al. November 17, 2	2009-11-17
Applications of cascading DSP slices Grant 7,567,997 - Simkins , et al. July 28, 2	2009-07-28
Formation of a hybrid integrated circuit device App 20090160482 - Karp; James ; et al.	2009-06-25
Method and apparatus for communication within a programmable device using serial transceivers Grant 7,546,408 - Donlin , et al. June 9, 2	2009-06-09
Integrated circuit with through-die via interface for die stacking Grant 7,518,398 - Rahman , et al. April 14, 2	2009-04-14
Timing analysis for programmable logic devices fabricated in different Fabs Grant 7,509,610 - New March 24, 2	2009-03-24
Arithmetic circuit with multiplexed addend inputs Grant 7,480,690 - Simkins , et al. January 20, 2	2009-01-20
Programmable logic device with cascading DSP slices Grant 7,472,155 - Simkins , et al. December 30, 2	2008-12-30
Programmable logic device with pipelined DSP slices Grant 7,467,175 - Simkins , et al. December 16, 2	2008-12-16
Mathematical circuit with dynamic rounding Grant 7,467,177 - Simkins , et al. December 16, 2	2008-12-16
Method and apparatus for communication within an integrated circuit Grant 7,301,824 - New November 27, 2	2007-11-27
Configurable logic element with expander structures Grant 7,248,073 - New , et al. July 24, 2	2007-07-24
Routing with derivative frame awareness to minimize device programming time and test cost Grant 7,240,320 - Trimberger , et al. July 3, 2	2007-07-03
Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames Grant 7,191,342 - New , et al. March 13, 2	2007-03-13
Configurable logic element with expander structures App 20070035328 - New; Bernard J. ; et al.	2007-02-15
Digital signal processing circuit having a SIMD circuit App 20060288069 - Simkins; James M. ; et al.	2006-12-21
Digital signal processing circuit having a pattern circuit for determining termination conditions App 20060288070 - Vadi; Vasisht Mantra ; et al.	2006-12-21
Reconfigurable multi-stage crossbar Grant 7,149,996 - Lysaght , et al. December 12, 2	2006-12-12
Configurable logic element with expander structures Grant 7,145,360 - New , et al. December 5, 2	2006-12-05
FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same Grant 7,138,828 - New November 21, 2	2006-11-21
Digital signal processing circuit having an adder circuit with carry-outs App 20060230096 - Thendean; John M. ; et al.	2006-10-12
Digital signal processing circuit having a pre-adder circuit App 20060230095 - Simkins; James M. ; et al.	2006-10-12
Digital signal processing circuit having input register blocks App 20060230094 - Simkins; James M. ; et al.	2006-10-12
Architectural floorplan for a digital signal processing circuit App 20060230092 - Ching; Alvin Y. ; et al.	2006-10-12
Digital signal processing circuit having a pattern detector circuit for convergent rounding App 20060230093 - New; Bernard J. ; et al.	2006-10-12
Digital signal processing block having a wide multiplexer App 20060212499 - New; Bernard J. ; et al.	2006-09-21
Arithmetic logic unit circuit App 20060206557 - Wong; Anna Wing Wah ; et al.	2006-09-14
Method and apparatus for designing custom programmable logic devices Grant 7,107,560 - New September 12, 2	2006-09-12
Digital signal processing circuit having a pattern detector circuit App 20060195496 - Vadi; Vasisht Mantra ; et al.	2006-08-31
Multi-speed delay-locked loop Grant 7,098,710 - New , et al. August 29, 2	2006-08-29
Digital signal processing element having an arithmetic logic unit App 20060190516 - Simkins; James M. ; et al.	2006-08-24
Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit Grant 7,068,072 - New , et al. June 27, 2	2006-06-27
Method and apparatus for communication within a programmable logic device using serial transceivers Grant 7,062,586 - Donlin , et al. June 13, 2	2006-06-13
FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same Grant 6,960,934 - New November 1, 2	2005-11-01
Method and apparatus for configuring a programmable logic device using a master JTAG port Grant 6,948,147 - New , et al. September 20, 2	2005-09-20
FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same Grant 6,930,510 - New August 16, 2	2005-08-16
Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice Grant 6,917,219 - New July 12, 2	2005-07-12
Mathematical circuit with dynamic rounding App 20050144213 - Simkins, James M. ; et al.	2005-06-30
Arithmetic circuit with multiplexed addend inputs App 20050144216 - Simkins, James M. ; et al.	2005-06-30
Programmable logic device with pipelined DSP slices App 20050144211 - Simkins, James M. ; et al.	2005-06-30
Programmable logic device with dynamic DSP architecture App 20050144210 - Simkins, James M. ; et al.	2005-06-30
Programmable logic device with cascading DSP slices App 20050144212 - Simkins, James M. ; et al.	2005-06-30
Applications of cascading DSP slices App 20050144215 - Simkins, James M. ; et al.	2005-06-30
Multi-chip module including embedded transistors within the substrate Grant 6,911,730 - New June 28, 2	2005-06-28
Configurable logic element with expander structures App 20050062498 - New, Bernard J. ; et al.	2005-03-24
FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same App 20050040851 - New, Bernard J.	2005-02-24
FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same App 20050039155 - New, Bernard J.	2005-02-17
Method and apparatus for communication within a programmable logic device using serial transceivers App 20050021749 - Donlin, Adam P. ; et al.	2005-01-27
Configurable logic element with expander structures Grant 6,847,229 - New , et al. January 25, 2	2005-01-25
Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit App 20040268286 - New, Bernard J. ; et al.	2004-12-30
Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice App 20040178819 - New, Bernard J.	2004-09-16
FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same App 20040174187 - New, Bernard J.	2004-09-09
Filter accelerator for a digital signal processor Grant 6,788,738 - New September 7, 2	2004-09-07
Dual-edge-correcting clock synchronization circuit Grant 6,720,810 - New April 13, 2	2004-04-13
Configurable logic element with expander structures App 20040032283 - New, Bernard J. ; et al.	2004-02-19
Configurable logic element with expander structures Grant 6,630,841 - New , et al. October 7, 2	2003-10-07
Configurable logic block for PLD with logic gate for combining output with another configurable logic block Grant 6,603,332 - Kaviani , et al. August 5, 2	2003-08-05
Method and apparatus for incorporating a multiplier into an FPGA Grant 6,573,749 - New , et al. June 3, 2	2003-06-03
Anti-aliasing filter with automatic cutoff frequency adaptation Grant 6,492,922 - New December 10, 2	2002-12-10
Configurable logic element with expander structures App 20020125910 - New, Bernard J. ; et al.	2002-09-12
Configurable logic block for PLD with logic gate for combining output with another configurable logic block App 20020079921 - Kaviani, Alireza S. ; et al.	2002-06-27
Configurable lookup table for programmable logic devices Grant 6,400,180 - Wittig , et al. June 4, 2	2002-06-04
Configurable logic element with expander structures Grant 6,396,302 - New , et al. May 28, 2	2002-05-28
Method and apparatus for incorporating a multiplier into an FPGA App 20020057104 - New, Bernard J. ; et al.	2002-05-16
Multiplexer for implementing logic functions in a programmable logic device Grant 6,362,648 - New , et al. March 26, 2	2002-03-26
Method and apparatus for incorporating a multiplier into an FPGA Grant 6,362,650 - New , et al. March 26, 2	2002-03-26
Dedicated function fabric for use in field programmable gate arrays Grant 6,346,824 - New February 12, 2	2002-02-12
Configurable logic element with expander structures App 20010045844 - New, Bernard J. ; et al.	2001-11-29
Configurable lookup table for programmable logic devices App 20010030555 - Witting, Ralph D. ; et al.	2001-10-18
Programmable logic device having configurable logic blocks with user-accessible input multiplexers Grant 6,292,019 - New , et al. September 18, 2	2001-09-18
Logic structure and circuit for fast carry Grant 6,288,570 - New September 11, 2	2001-09-11
Field programmable gate array with mask programmable I/O drivers Grant 6,242,945 - New June 5, 2	2001-06-05
Wide logic gate implemented in an FPGA configurable logic element Grant 6,201,410 - New , et al. March 13, 2	2001-03-13
Programmable logic device having a composable memory array overlaying a CLB array Grant 6,184,709 - New February 6, 2	2001-02-06
FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA Grant 6,172,520 - Lawman , et al. January 9, 2	2001-01-09
Combined tristate/carry logic mechanism Grant 6,154,052 - New November 28, 2	2000-11-28
Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch Grant 6,154,053 - New November 28, 2	2000-11-28
Multiplier fabric for use in field programmable gate arrays Grant 6,154,049 - New November 28, 2	2000-11-28
Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM Grant 6,150,839 - New , et al. November 21, 2	2000-11-21
FPGA CLE with two independent carry chains Grant 6,107,827 - Young , et al. August 22, 2	2000-08-22
Field programmable gate array with mask programmable I/O drivers Grant 6,091,262 - New July 18, 2	2000-07-18
Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM Grant 6,091,263 - New , et al. July 18, 2	2000-07-18
Programmable power reduction in a clock-distribution circuit Grant 6,072,348 - New , et al. June 6, 2	2000-06-06
Partially reconfigurable FPGA and method of operating same Grant 6,057,704 - New , et al. May 2, 2	2000-05-02
Method and apparatus for controlling the partial reconfiguration of a field programmable gate array Grant 6,046,603 - New April 4, 2	2000-04-04
Microprocessor with distributed registers accessible by programmable logic device Grant 6,026,481 - New , et al. February 15, 2	2000-02-15
Multiplexer enhanced configurable logic block Grant 6,020,756 - New February 1, 2	2000-02-01
Field programmable gate array with dedicated computer bus interface and method for configuring both Grant 6,011,407 - New January 4, 2	2000-01-04
Phase-locked loop architecture for a programmable logic device Grant 5,999,025 - New December 7, 1	1999-12-07
Configurable logic element with fast feedback paths Grant 5,963,050 - Young , et al. October 5, 1	1999-10-05
Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization Grant 5,956,748 - New September 21, 1	1999-09-21
Method and structure for providing fast conditional sum in a field programmable gate array Grant 5,898,319 - New April 27, 1	1999-04-27
Method and circuit for using a function generator of a programmable logic device to implement carry logic functions Grant 5,818,255 - New , et al. October 6, 1	1998-10-06
Composable memory array for a programmable logic device and method for implementing same Grant 5,796,269 - New August 18, 1	1998-08-18
Fast carry-out scheme in a field programmable gate array Grant 5,675,262 - Duong , et al. October 7, 1	1997-10-07
Method and structure for providing fast propagation of a carry signal in a field programmable gate array Grant 5,629,886 - New May 13, 1	1997-05-13
Input synchronization mechanism for inside/outside clock Grant 5,578,946 - Carberry , et al. November 26, 1	1996-11-26
Programmable sequencher having internal components which are microprocessor read/write interfacable Grant 5,553,301 - New , et al. September 3, 1	1996-09-03
Circuit for fast carry and logic Grant 5,481,206 - New , et al. January 2, 1	1996-01-02
Structure and method for configuration of a field programmable gate array Grant 5,450,022 - New September 12, 1	1995-09-12
Logic structure and circuit for fast carry Grant 5,349,250 - New September 20, 1	1994-09-20
Floating point add/subtract and multiplying assemblies sharing common normalization, rounding and exponential apparatus Grant 4,943,940 - New July 24, 1	1990-07-24
High throughput extended-precision multiplier Grant 4,809,212 - New , et al. February 28, 1	1989-02-28
Parallel multiplier array with foreshortened sign extension Grant 4,748,582 - New , et al. May 31, 1	1988-05-31
Method and apparatus for generating and summing the products of pairs of numbers Grant 4,692,888 - New September 8, 1	1987-09-08
Method and apparatus for sequencing addresses of a fast Fourier transform array Grant 4,393,457 - New July 12, 1	1983-07-12
Bit slice microprogrammable processor for signal processing applications Grant 4,393,468 - New July 12, 1	1983-07-12