Neves; Jose Luis Pontes Correia
Patent Applications and Registrations
Patent applications and USPTO patent grants for Neves; Jose Luis Pontes Correia.The latest application filed is for "method of automating creation of a clock control distribution network in an integrated circuit floorplan".
- Neves; Jose Luis Pontes Correia - Poughkeepsie NY
- Neves; Jose Luis Pontes Correia - Wappinger Falls NY
| Patent | Date |
|---|---|
| Method of automating creation of a clock control distribution network in an integrated circuit floorplan Grant 7,979,838 - Berry , et al. July 12, 2 | 2011-07-12 |
| System for improving a logic circuit and associated methods Grant 7,895,539 - Carney , et al. February 22, 2 | 2011-02-22 |
| Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design Grant 6,651,230 - Cohn , et al. November 18, 2 | 2003-11-18 |
| Apparatus and method for buffer library selection for use in buffer insertion Grant 6,560,752 - Alpert , et al. May 6, 2 | 2003-05-06 |
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