Nevers; Yannick Marc
Patent Applications and Registrations
Patent applications and USPTO patent grants for Nevers; Yannick Marc.The latest application filed is for "dynamic memory scrambling".
- Nevers; Yannick Marc - Sassenage FR
- Nevers; Yannick Marc - Grenoble FR
| Patent | Date |
|---|---|
| Dynamic memory scrambling Grant 10,558,585 - Nevers , et al. Feb | 2020-02-11 |
| Dynamic Memory Scrambling App 20170147509 - NEVERS; Yannick Marc ; et al. | 2017-05-25 |
| Low power latching circuits Grant 8,941,428 - Javerliac , et al. January 27, 2 | 2015-01-27 |
| Low Power Latching Circuits App 20140218089 - JAVERLIAC; Virgile ; et al. | 2014-08-07 |
| Low Power Latching Circuits App 20140125392 - JAVERLIAC; Virgile ; et al. | 2014-05-08 |
| Generating ROM bit cell arrays Grant 8,422,262 - Nevers , et al. April 16, 2 | 2013-04-16 |
| Generating ROM bit cell arrays App 20110249481 - Nevers; Yannick Marc ; et al. | 2011-10-13 |
| Generating ROM bit cell arrays Grant 7,961,490 - Nevers , et al. June 14, 2 | 2011-06-14 |
| Read only memory cell for storing a multiple bit value Grant 7,936,578 - Nevers , et al. May 3, 2 | 2011-05-03 |
| Read only memory cell for storing a multiple bit value App 20110051487 - Nevers; Yannick Marc ; et al. | 2011-03-03 |
| Generating ROM bit cell arrays App 20100177544 - Nevers; Yannick Marc ; et al. | 2010-07-15 |
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