Neppl; Franz

Patent Applications and Registrations

Patent applications and USPTO patent grants for Neppl; Franz.The latest application filed is for "method for detaching chips from a wafer".

Company Profile

0.20.0

Neppl; Franz - Ottobrunn DE
Neppl; Franz - Munich DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for detaching chips from a wafer Grant 5,597,766 - Neppl January 28, 1	1997-01-28
Integrated circuit containing bi-polar and complementary MOS transistors on a common substrate and method for the manufacture thereof Grant 5,100,811 - Winnerl , et al. March 31, 1	1992-03-31
Method of making an integrated circuit comprising load resistors arranged on the field oxide zones which separate the active transistor zones Grant 5,013,678 - Winnerl , et al. May 7, 1	1991-05-07
Method for self-aligned manufacture of contacts between interconnects contained in wiring levels arranged above one another in an integrated circuit Grant 4,960,489 - Roeska , et al. October 2, 1	1990-10-02
Integrated semiconductor circuit having an external contacting track level consisting of aluminum or of an aluminum alloy Grant 4,912,543 - Neppl , et al. March 27, 1	1990-03-27
Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches Grant 4,906,585 - Neppl , et al. March 6, 1	1990-03-06
Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit Grant 4,885,617 - Mazure-Espejo , et al. December 5, 1	1989-12-05
Circuit containing integrated bipolar and complementary MOS transistors on a common substrate Grant 4,884,117 - Neppl , et al. November 28, 1	1989-11-28
Semiconductor circuit containing integrated bipolar and MOS transistors on a chip and method of producing same Grant 4,874,717 - Neppl , et al. October 17, 1	1989-10-17
Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate Grant 4,855,245 - Neppl , et al. August 8, 1	1989-08-08
Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate Grant 4,782,033 - Gierisch , et al. November 1, 1	1988-11-01
Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing Grant 4,761,384 - Neppl , et al. August 2, 1	1988-08-02
Method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories Grant 4,740,479 - Neppl , et al. * April 26, 1	1988-04-26
Integrated semiconductor circuit including a tantalum silicide diffusion barrier Grant 4,680,612 - Hieber , et al. July 14, 1	1987-07-14
Integrated MOS transistors having a gate metallization composed of tantalum or niobium or their silicides Grant 4,673,968 - Hieber , et al. June 16, 1	1987-06-16
Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon Grant 4,640,844 - Neppl , et al. * February 3, 1	1987-02-03
Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation Grant 4,603,472 - Schwabe , et al. August 5, 1	1986-08-05
Method for manufacturing VLSI complementary MOS field effect circuits Grant 4,525,378 - Schwabe , et al. June 25, 1	1985-06-25
Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors Grant 4,510,670 - Schwabe , et al. April 16, 1	1985-04-16
Method of making MOS device using metal silicides or polysilicon for gates and impurity source for active regions Grant 4,505,027 - Schwabe , et al. March 19, 1	1985-03-19

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