Nelson; Bradley S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nelson; Bradley S..The latest application filed is for "clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic".

Company Profile

0.14.16

Nelson; Bradley S. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic Grant 8,238,190 - Ja , et al. August 7, 2	2012-08-07
Methods and arrangements to model an asynchronous interface Grant 7,995,619 - Ja , et al. August 9, 2	2011-08-09
Modeling asynchronous behavior from primary inputs and latches Grant 7,885,801 - Hidvegi , et al. February 8, 2	2011-02-08
Accurately modeling an asynchronous interface using expanded logic elements Grant 7,877,717 - Chu , et al. January 25, 2	2011-01-25
Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation Grant 7,870,528 - Ja , et al. January 11, 2	2011-01-11
Program product for providing a configuration specification language supporting incompletely specified configuration entities Grant 7,519,524 - Nelson , et al. April 14, 2	2009-04-14
Method for modeling metastability decay through latches in an integrated circuit model Grant 7,484,192 - Ja , et al. January 27, 2	2009-01-27
Method for asynchronous clock modeling in an integrated circuit simulation Grant 7,484,196 - Ja , et al. January 27, 2	2009-01-27
Clock-gated Model Transformation For Asynchronous Testing Of Logic Targeted For Free-running, Data-gated Logic App 20080301603 - Ja; Yee ; et al.	2008-12-04
Modeling Asynchronous Behavior From Primary Inputs And Latches App 20080295052 - Hidvegi; Zoltan T. ; et al.	2008-11-27
Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic Grant 7,453,759 - Ja , et al. November 18, 2	2008-11-18
Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation Grant 7,448,015 - Ja , et al. November 4, 2	2008-11-04
Modeling asynchronous behavior from primary inputs and latches Grant 7,447,620 - Hidvegi , et al. November 4, 2	2008-11-04
Method And System For Unfolding/replicating Logic Paths To Facilitate Modeling Of Metastable Value Propagation App 20080270966 - Ja; Yee ; et al.	2008-10-30
Program Product For Providing A Configuration Specification Language Supporting Incompletely Specified Configuration Entities App 20080256135 - NELSON; BRADLEY S. ; et al.	2008-10-16
Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities Grant 7,426,461 - Nelson , et al. September 16, 2	2008-09-16
Methods and Arrangements to Model an Asynchronous Interface App 20080192645 - Ja; Yee ; et al.	2008-08-14
System and Method for Asynchronous Clock Modeling in an Integrated Circuit Simulation App 20080072197 - Ja; Yee ; et al.	2008-03-20
System and Method for Modeling Metastability Decay Through Latches in an Integrated Circuit Model App 20080072188 - Ja; Yee ; et al.	2008-03-20
System and Method for Accurately Modeling an Asynchronous Interface using Expanded Logic Elements App 20080040695 - Chu; Bing-Lun ; et al.	2008-02-14
System and method for unfolding/replicating logic paths to facilitate propagation delay modeling Grant 7,302,659 - Ja , et al. November 27, 2	2007-11-27
Method and System for Unfolding/Replicating Logic Paths to Facilitate Modeling of Metastable Value Propagation App 20070271542 - Ja; Yee ; et al.	2007-11-22
System and method for accurately modeling an asynchronous interface using expanded logic elements Grant 7,299,436 - Chu , et al. November 20, 2	2007-11-20
Clock-Gated Model Transformation for Asynchronous Testing of Logic Targeted for Free-Running, Data-Gated Logic App 20070253275 - Ja; Yee ; et al.	2007-11-01
Method For Modeling Metastability Decay Using Fence Logic Insertion App 20070244685 - Ja; Yee ; et al.	2007-10-18
Modeling asynchronous behavior from primary inputs and latches App 20070198238 - Hidvegi; Zoltan T. ; et al.	2007-08-23
Methods and arrangements to model an asynchronous interface App 20070098020 - Ja; Yee ; et al.	2007-05-03
System and method for unfolding/replicating logic paths to facilitate propagation delay modeling App 20060190883 - Ja; Yee ; et al.	2006-08-24
System and method for accurately modeling an asynchronous interface using expanded logic elements App 20060190858 - Chu; Bing-Lun ; et al.	2006-08-24
Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities App 20060004556 - Nelson; Bradley S. ; et al.	2006-01-05

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