loadpatents
Patent applications and USPTO patent grants for Neilson; John M. S..The latest application filed is for "high voltage mosfet structure".
Patent | Date |
---|---|
High voltage mosfet structure Grant 6,081,009 - Neilson June 27, 2 | 2000-06-27 |
High voltage semiconductor structure Grant 6,066,878 - Neilson May 23, 2 | 2000-05-23 |
Apparatus and method for increasing breakdown voltage ruggedness in semiconductor devices Grant 5,424,563 - Temple , et al. June 13, 1 | 1995-06-13 |
Mesh geometry for MOS-gated semiconductor devices Grant 5,399,892 - Neilson , et al. March 21, 1 | 1995-03-21 |
Power FET with gate segments covering drain regions disposed in a hexagonal pattern Grant 5,323,036 - Neilson , et al. June 21, 1 | 1994-06-21 |
Power FET having reduced threshold voltage Grant 5,218,220 - Neilson , et al. June 8, 1 | 1993-06-08 |
Power VDMOSFET with schottky on lightly doped drain of lateral driver FET Grant 5,164,802 - Jones , et al. November 17, 1 | 1992-11-17 |
Power MOSFET Grant 5,095,343 - Klodzinski , et al. March 10, 1 | 1992-03-10 |
Power MOSFET transistor circuit with active clamp Grant 5,079,608 - Wodarczyk , et al. January 7, 1 | 1992-01-07 |
Power MOSFET transistor circuit Grant 5,023,692 - Wodarczyk , et al. June 11, 1 | 1991-06-11 |
MOSFET with reduced bipolar effects Grant 4,639,762 - Neilson , et al. January 27, 1 | 1987-01-27 |
MOSFET with perimeter channel Grant 4,532,534 - Ford , et al. July 30, 1 | 1985-07-30 |
Transistor with integrated diode and resistor Grant 4,398,206 - Neilson August 9, 1 | 1983-08-09 |
Method of treating SiPOS passivated high voltage semiconductor device Grant 4,297,149 - Koons , et al. October 27, 1 | 1981-10-27 |
Semiconductor thyristor device having integral ballast means Grant 4,292,646 - Assour , et al. September 29, 1 | 1981-09-29 |
Method of diffusing aluminum into monocrystalline silicon Grant 4,199,386 - Rosnowski , et al. April 22, 1 | 1980-04-22 |
Semiconductor device Grant 4,158,206 - Neilson June 12, 1 | 1979-06-12 |
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