| Patent | Date |
|---|
High-level synthesis implementation of data structures in hardware
Grant 11,314,911 - Du , et al. April 26, 2 | 2022-04-26 |
High-level synthesis vector library for single-instruction multiple data programming and electronic system design
Grant 11,238,199 - Isoard , et al. February 1, 2 | 2022-02-01 |
Enabling integrity and authenticity of design data
Grant 11,042,610 - Neema , et al. June 22, 2 | 2021-06-22 |
Unified container for hardware and software binaries
Grant 10,956,241 - Neema , et al. March 23, 2 | 2021-03-23 |
Updating firmware for programmable integrated circuits in computing environments
Grant 10,922,068 - Radjabi , et al. February 16, 2 | 2021-02-16 |
Streaming platform flow and architecture for an integrated circuit
Grant 10,924,430 - Thyamagondlu , et al. February 16, 2 | 2021-02-16 |
Embedded scheduling of hardware resources for hardware acceleration
Grant 10,877,766 - Soe , et al. December 29, 2 | 2020-12-29 |
Unified address space for multiple hardware accelerators using dedicated low latency links
Grant 10,802,995 - Singh , et al. October 13, 2 | 2020-10-13 |
Customizable debug and profile monitoring of reconfigurable systems
Grant 10,713,404 - Schumacher , et al. | 2020-07-14 |
Streaming Platform Flow And Architecture
App 20200153756 - Thyamagondlu; Chandrasekhar S. ; et al. | 2020-05-14 |
Address-based waveform database architecture
Grant 10,642,811 - Liddell , et al. | 2020-05-05 |
Unified Address Space For Multiple Hardware Accelerators Using Dedicated Low Latency Links
App 20200081850 - Singh; Sarabjeet ; et al. | 2020-03-12 |
Embedded Scheduling Of Hardware Resources For Hardware Acceleration
App 20190361708 - Soe; Soren T. ; et al. | 2019-11-28 |
Mixed-language simulation
Grant 10,296,673 - Ghosh , et al. | 2019-05-21 |
Performance and memory efficient modeling of HDL ports for simulation
Grant 9,223,910 - Ghosh , et al. December 29, 2 | 2015-12-29 |
Compilation and simulation of a circuit design
Grant 9,135,384 - Santan , et al. September 15, 2 | 2015-09-15 |
Net sensitivity ranges for detection of simulation events
Grant 9,117,043 - Huang , et al. August 25, 2 | 2015-08-25 |
Verification and debugging using heterogeneous simulation models
Grant 8,868,396 - Shirazi , et al. October 21, 2 | 2014-10-21 |
Mixed-language simulation
Grant 8,838,431 - Mihalache , et al. September 16, 2 | 2014-09-16 |
Compilation and simulation of a circuit design
Grant 8,516,413 - Deshpande , et al. August 20, 2 | 2013-08-20 |
Scheduling processes in simulation of a circuit design
Grant 8,495,539 - Mihalache , et al. July 23, 2 | 2013-07-23 |
Generating simulation code from a specification of a circuit design
Grant 8,447,581 - Roth , et al. May 21, 2 | 2013-05-21 |
Compilation and simulation of a circuit design
Grant 8,418,095 - Neema , et al. April 9, 2 | 2013-04-09 |
Generating a simulation model of a circuit design
Grant 8,327,311 - Neema , et al. December 4, 2 | 2012-12-04 |
Simulation and emulation of a circuit design
Grant 8,265,918 - Neema , et al. September 11, 2 | 2012-09-11 |
Method and system for transforming fork-join blocks in a hardware description language (HDL) specification
Grant 8,161,436 - Neema April 17, 2 | 2012-04-17 |
Securing circuit designs within circuit design tools
Grant 8,074,077 - Neema , et al. December 6, 2 | 2011-12-06 |
Event-driven simulation of IP using third party event-driven simulators
Grant 7,721,090 - Deepak , et al. May 18, 2 | 2010-05-18 |
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