Nayak; Neeraj P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nayak; Neeraj P..The latest application filed is for "isolation circuit for a digital-to-analog converter".

Company Profile

0.5.6

Nayak; Neeraj P. - Plano TX
Nayak; Neeraj P. - Richardson TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Isolation circuit for a digital-to-analog converter Grant 8,525,716 - Bhatia , et al. September 3, 2	2013-09-03
Isolation Circuit For A Digital-to-analog Converter App 20130169458 - BHATIA; Karan S. ; et al.	2013-07-04
Bist DDR memory interface circuit and method for testing the same Grant 8,035,407 - Jarboe, Jr. , et al. October 11, 2	2011-10-11
Bist Ddr Memory Interface Circuit And Method For Testing The Same App 20110176374 - Jarboe, JR.; James Michael ; et al.	2011-07-21
BIST DDR memory interface circuit and method for testing the same Grant 7,940,066 - Jarboe, Jr. , et al. May 10, 2	2011-05-10
Bist Ddr Memory Interface Circuit And Method For Testing The Same App 20110026343 - Jarboe, JR.; James Michael ; et al.	2011-02-03
Bist DDR memory interface circuit and method for self-testing the same using phase relationship between a data signal and a data strobe signal Grant 7,834,615 - Jarboe, Jr. , et al. November 16, 2	2010-11-16
Bist Ddr Memory Interface Circuit And Method For Testing The Same App 20090009206 - Jarboe, JR.; James Michael ; et al.	2009-01-08
Bist Ddr Memory Interface Circuit And Method For Testing The Same App 20090013228 - JARBOE, JR.; JAMES MICHAEL ; et al.	2009-01-08

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