Nayak; Deepak Kumar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nayak; Deepak Kumar.The latest application filed is for "beam selection for cellular access nodes".

Company Profile

5.18.4

Nayak; Deepak Kumar - Bangalore IN
Nayak; Deepak Kumar - Seattle WA
Nayak; Deepak Kumar - Fremont CA
Nayak; Deepak Kumar - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Beam selection for cellular access nodes Grant 11,425,591 - Maggi , et al. August 23, 2	2022-08-23
Beam Selection For Cellular Access Nodes App 20220256389 - MAGGI; Lorenzo ; et al.	2022-08-11
Efficient data generation for beam pattern optimization Grant 11,012,133 - Capdevielle , et al. May 18, 2	2021-05-18
Efficient Data Generation For Beam Pattern Optimization App 20210083737 - CAPDEVIELLE; Veronique ; et al.	2021-03-18
Taxonomy generation with statistical analysis and auditing Grant 10,909,144 - Dutta , et al. February 2, 2	2021-02-02
Classification accuracy estimation Grant 10,726,060 - Dutta , et al.	2020-07-28
Techniques for generating machine learning training data Grant 10,339,470 - Dutta , et al.	2019-07-02
High mobility PMOS and NMOS devices having Si--Ge quantum wells Grant 9,406,799 - Nayak August 2, 2	2016-08-02
HIGH MOBILITY PMOS AND NMOS DEVICES HAVING Si-Ge QUANTUM WELLS App 20160111539 - Nayak; Deepak Kumar	2016-04-21
Semiconductor device with improved trenches Grant 8,120,075 - Luo , et al. February 21, 2	2012-02-21
Semiconductor device with backfilled isolation Grant 7,936,006 - Luo , et al. May 3, 2	2011-05-03
Strain-silicon CMOS using etch-stop layer and method of manufacture Grant 7,875,543 - Luo , et al. January 25, 2	2011-01-25
Semiconductor device and process for improved etch control of strained silicon alloy trenches Grant 7,851,313 - Luo , et al. December 14, 2	2010-12-14
Method of and circuit for protecting a transistor formed on a die Grant 7,772,093 - Luo , et al. August 10, 2	2010-08-10
Method of fabricating strain-silicon CMOS Grant 7,670,923 - Nayak , et al. March 2, 2	2010-03-02
CMOS device with stressed sidewall spacers Grant 7,655,991 - Nayak , et al. February 2, 2	2010-02-02
Method of and circuit for protecting a transistor formed on a die App 20090108337 - Luo; Yuhao ; et al.	2009-04-30
Method of forming silicide gate with interlayer Grant 7,429,526 - Nayak , et al. September 30, 2	2008-09-30
Method of fabricating strain-silicon CMOS Grant 7,429,775 - Nayak , et al. September 30, 2	2008-09-30
Strain-silicon CMOS using etch-stop layer and method of manufacture Grant 7,423,283 - Luo , et al. September 9, 2	2008-09-09
Strain-silicon CMOS with dual-stressed film Grant 7,214,629 - Luo , et al. May 8, 2	2007-05-08
Method and circuit for detecting boron ("B") in a semiconductor device using threshold voltage ("V") fluence test Grant 5,757,204 - Nayak , et al. May 26, 1	1998-05-26

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