loadpatents
name:-0.018203973770142
name:-0.013206005096436
name:-0.00035619735717773
Naujok; Markus Patent Filings

Naujok; Markus

Patent Applications and Registrations

Patent applications and USPTO patent grants for Naujok; Markus.The latest application filed is for "passivated copper chip pads".

Company Profile
0.13.14
  • Naujok; Markus - Dresden N/A DE
  • Naujok; Markus - Hsinchu TW
  • Naujok; Markus - Hopewell Junction NY
  • Naujok; Markus - Hsin-Chu TW
  • Naujok, Markus - Hsin-Chu City TW
  • Naujok; Markus - Wappingers Falls NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor devices and structures thereof
Grant 9,401,322 - Naujok , et al. July 26, 2
2016-07-26
Passivated copper chip pads
Grant 9,373,596 - Goebel , et al. June 21, 2
2016-06-21
Passivated Copper Chip Pads
App 20140295661 - Goebel; Thomas ;   et al.
2014-10-02
Passivated copper chip pads
Grant 8,822,324 - Goebel , et al. September 2, 2
2014-09-02
Passivated Copper Chip Pads
App 20130224946 - Goebel; Thomas ;   et al.
2013-08-29
Methods of manufacturing semiconductor devices
Grant 8,148,235 - Naujok , et al. April 3, 2
2012-04-03
Semiconductor Devices and Structures Thereof
App 20110278730 - Naujok; Markus ;   et al.
2011-11-17
Semiconductor devices and structures thereof
Grant 8,013,364 - Naujok , et al. September 6, 2
2011-09-06
Methods of Manufacturing Semiconductor Devices
App 20100144112 - Naujok; Markus ;   et al.
2010-06-10
Semiconductor Devices and Structures Thereof
App 20100032841 - Naujok; Markus ;   et al.
2010-02-11
Methods of manufacturing semiconductor devices and structures thereof
Grant 7,629,225 - Naujok , et al. December 8, 2
2009-12-08
Passivated Copper Chip Pads
App 20090200675 - Goebel; Thomas ;   et al.
2009-08-13
Methods of forming integrated circuit devices having metal interconnect layers therein
Grant 7,282,451 - Hong , et al. October 16, 2
2007-10-16
Polishing methods and apparatus
Grant 7,201,634 - Naujok , et al. April 10, 2
2007-04-10
Methods of forming integrated circuit devices having metal interconnect layers therein
App 20070045123 - Hong; Duk Ho ;   et al.
2007-03-01
Methods of manufacturing semiconductor devices and structures thereof
App 20060281295 - Naujok; Markus ;   et al.
2006-12-14
Dual damascene structure and method
Grant 7,091,612 - Kumar , et al. August 15, 2
2006-08-15
Composite intermetal dielectric structure including low-k dielectric material
Grant 7,041,574 - Kim , et al. May 9, 2
2006-05-09
Chemical mechanical polish with multi-zone abrasive-containing matrix
App 20060079159 - Naujok; Markus ;   et al.
2006-04-13
Dual damascene structure and method
App 20050077628 - Kumar, Kaushik ;   et al.
2005-04-14
Composite intermetal dielectric structure including low-k dielectric material
App 20040259273 - Kim, Sun-Oo ;   et al.
2004-12-23
Composite low-k dielectric structure
App 20040248400 - Kim, Sun-Oo ;   et al.
2004-12-09
Wafer polishing with counteraction of centrifugal forces on polishing slurry
App 20040152402 - Naujok, Markus ;   et al.
2004-08-05
Finishing pad design for multidirectional use
Grant 6,761,620 - Naujok July 13, 2
2004-07-13
Novel finishing pad design for multidirectional use
App 20040053570 - Naujok, Markus
2004-03-18
Finishing pad design for multidirectional use
Grant 6,602,123 - Naujok August 5, 2
2003-08-05

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