loadpatents
Patent applications and USPTO patent grants for Natarajan; Sanjay.The latest application filed is for "conformal high concentration boron doping of semiconductors".
Patent | Date |
---|---|
Self-aligned contact and contact over active gate structures Grant 11,437,273 - Shusterman , et al. September 6, 2 | 2022-09-06 |
Conformal High Concentration Boron Doping Of Semiconductors App 20220246432 - Gandikota; Srinivas ;   et al. | 2022-08-04 |
Integrated CMOS Source Drain Formation With Advanced Control App 20220199804 - Colombeau; Benjamin ;   et al. | 2022-06-23 |
Conformal high concentration boron doping of semiconductors Grant 11,328,928 - Gandikota , et al. May 10, 2 | 2022-05-10 |
Multi Color Stack For Self Aligned Dual Pattern Formation For Multi Purpose Device Structures App 20220130722 - PARIKH; Suketu Arun ;   et al. | 2022-04-28 |
Integrated CMOS source drain formation with advanced control Grant 11,309,404 - Colombeau , et al. April 19, 2 | 2022-04-19 |
3d Dram Structure With High Mobility Channel App 20220108728 - Kang; Chang Seok ;   et al. | 2022-04-07 |
3D dram structure with high mobility channel Grant 11,295,786 - Kang , et al. April 5, 2 | 2022-04-05 |
Method Of Fabricating A Semiconductor Device Having Reduced Contact Resistance App 20220093749 - THAREJA; Gaurav ;   et al. | 2022-03-24 |
Gap Fill Methods For Dram App 20220068935 - Panda; Priyadarshi ;   et al. | 2022-03-03 |
Stacked Transistor Device App 20220068917 - Parikh; Suketu Arun ;   et al. | 2022-03-03 |
DRAM Capacitor Module App 20220013624 - Mitra; Uday ;   et al. | 2022-01-13 |
Selective Silicon Etch For Gate All Around Transistors App 20220005937 - Stolfi; Michael ;   et al. | 2022-01-06 |
Method of fabricating a semiconductor device having reduced contact resistance Grant 11,195,923 - Thareja , et al. December 7, 2 | 2021-12-07 |
3D-NAND mold Grant 11,189,635 - Kang , et al. November 30, 2 | 2021-11-30 |
Stacked transistor device Grant 11,177,254 - Parikh , et al. November 16, 2 | 2021-11-16 |
Gap fill methods of forming buried word lines in DRAM without forming bottom voids Grant 11,171,141 - Panda , et al. November 9, 2 | 2021-11-09 |
DRAM capacitor module Grant 11,164,938 - Mitra , et al. November 2, 2 | 2021-11-02 |
Semiconductor device, method of making a semiconductor device, and processing system Grant 11,152,479 - Thareja , et al. October 19, 2 | 2021-10-19 |
Processing system and method of forming a contact Grant 11,114,320 - Thareja , et al. September 7, 2 | 2021-09-07 |
Gate Contact Over Active Regions App 20210249270 - THAREJA; Gaurav ;   et al. | 2021-08-12 |
Gate contact over active processes Grant 11,004,687 - Thareja , et al. May 11, 2 | 2021-05-11 |
Methods and apparatus for smoothing dynamic random access memory bit line metal Grant 10,903,112 - Panda , et al. January 26, 2 | 2021-01-26 |
Method for creating a fully self-aligned via Grant 10,892,187 - Freed , et al. January 12, 2 | 2021-01-12 |
3d-nand Mold App 20200312874 - Kang; Chang Seok ;   et al. | 2020-10-01 |
DRAM Capacitor Module App 20200312953 - Mitra; Uday ;   et al. | 2020-10-01 |
Gap Fill Methods For Dram App 20200286897 - Panda; Priyadarshi ;   et al. | 2020-09-10 |
Self-aligned Contact And Contact Over Active Gate Structures App 20200279773 - Shusterman; Yuriy ;   et al. | 2020-09-03 |
Gate Contact Over Active Processes App 20200258744 - A1 | 2020-08-13 |
Semiconductor Device, Method Of Making A Semiconductor Device, And Processing System App 20200258997 - A1 | 2020-08-13 |
3d Dram Structure With High Mobility Channel App 20200251151 - Kind Code | 2020-08-06 |
Cap Layer For Bit Line Resistance Reduction App 20200235104 - Panda; Priyadarshi ;   et al. | 2020-07-23 |
Cap layer for bit line resistance reduction Grant 10,700,072 - Panda , et al. | 2020-06-30 |
Method Of Fabricating A Semiconductor Device Having Reduced Contact Resistance App 20200203490 - THAREJA; Gaurav ;   et al. | 2020-06-25 |
Processing System And Method Of Forming A Contact App 20200203481 - THAREJA; Gaurav ;   et al. | 2020-06-25 |
Cap Layer For Bit Line Resistance Reduction App 20200126996 - Panda; Priyadarshi ;   et al. | 2020-04-23 |
Methods And Apparatus For Smoothing Dynamic Random Access Memory Bit Line Metal App 20200126844 - PANDA; PRIYADARSHI ;   et al. | 2020-04-23 |
Stacked Transistor Device App 20200118996 - Parikh; Suketu Arun ;   et al. | 2020-04-16 |
Methods of producing fully self-aligned vias and contacts Grant 10,553,485 - Zhang , et al. Fe | 2020-02-04 |
Integrated CMOS Source Drain Formation With Advanced Control App 20200013878 - Colombeau; Benjamin ;   et al. | 2020-01-09 |
Method and apparatus for substrate fabrication Grant 10,529,602 - Panda , et al. J | 2020-01-07 |
Conformal High Concentration Boron Doping Of Semiconductors App 20190385851 - GANDIKOTA; SRINIVAS ;   et al. | 2019-12-19 |
Method For Creating A Fully Self-Aligned Via App 20190355620 - Freed; Regina ;   et al. | 2019-11-21 |
Methods Of Producing Fully Self-Aligned Vias And Contacts App 20180374750 - Zhang; Ying ;   et al. | 2018-12-27 |
Transistor with strain-inducing structure in channel Grant 7,473,591 - Cea , et al. January 6, 2 | 2009-01-06 |
Sacrificial capping layer for transistor performance enhancement App 20070004114 - Lee; Seok-Hee ;   et al. | 2007-01-04 |
Stepped tip junction with spacer layer Grant 7,112,859 - Ban , et al. September 26, 2 | 2006-09-26 |
Methods of optimization of implant conditions to minimize channeling and structures formed thereby App 20060202267 - Ranade; Pushkar ;   et al. | 2006-09-14 |
Methods of optimization of implant conditions to minimize channeling and structures formed thereby App 20060084248 - Ranade; Pushkar ;   et al. | 2006-04-20 |
Transistor with strain-inducing structure in channel App 20060084216 - Cea; Stephen M. ;   et al. | 2006-04-20 |
Transistor with strain-inducing structure in channel Grant 7,019,326 - Cea , et al. March 28, 2 | 2006-03-28 |
Stepped tip junction with spacer layer App 20050253192 - Ban, Ibrahim ;   et al. | 2005-11-17 |
Transistor with strain-inducing structure in channel App 20050106792 - Cea, Stephen M. ;   et al. | 2005-05-19 |
Forming polysilicon structures App 20040075119 - Natarajan, Sanjay ;   et al. | 2004-04-22 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.