Nassif; Sani Richard

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nassif; Sani Richard.The latest application filed is for "layout-specific classification and prioritization of recommended rules violations".

Company Profile

0.15.19

Nassif; Sani Richard - Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Visualizing sensitivity information in integrated circuit design Grant 8,914,272 - Gattiker , et al. December 16, 2	2014-12-16
Guiding design actions for complex failure modes Grant 8,595,664 - Gattiker , et al. November 26, 2	2013-11-26
Guiding design actions for complex failure modes Grant 8,595,665 - Gattiker , et al. November 26, 2	2013-11-26
Layout-specific classification and prioritization of recommended rules violations Grant 8,539,421 - Agarwal , et al. September 17, 2	2013-09-17
Dynamic Pin Access Maximization For Multi-patterning Lithography App 20130159955 - Ghaida; Rani Abou ; et al.	2013-06-20
Guiding Design Actions For Complex Failure Modes App 20130159946 - Gattiker; Anne Elizabeth ; et al.	2013-06-20
Guiding Design Actions For Complex Failure Modes App 20130159947 - GATTIKER; ANNE ELIZABETH ; et al.	2013-06-20
Visualizing Sensitivity Information In Integrated Circuit Design App 20130158953 - Gattiker; Anne Elizabeth ; et al.	2013-06-20
Layout-specific Classification And Prioritization Of Recommended Rules Violations App 20130159948 - Agarwal; Kanak Behari ; et al.	2013-06-20
Cost-effective And Reliable Utilities Distribution Network App 20130096976 - Alpert; Charles Jay ; et al.	2013-04-18
Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields App 20110173577 - Chuang; Ching-Te K. ; et al.	2011-07-14
Method and system for short-circuit current modeling in CMOS integrated circuits Grant 7,191,113 - Acar , et al. March 13, 2	2007-03-13
On-wafer method and apparatus for pre-processing measurements of process and environment-dependent circuit performance variables for statistical analysis Grant 7,171,333 - Nassif January 30, 2	2007-01-30
On-wafer method and apparatus for pre-processing measurements of process and environment-dependent circuit performance variables for statistical analysis App 20060235647 - Nassif; Sani Richard	2006-10-19
Decoupling capacitor sizing and placement Grant 6,898,769 - Nassif , et al. May 24, 2	2005-05-24
Method and system for power node current waveform modeling Grant 6,769,100 - Acar , et al. July 27, 2	2004-07-27
Method and apparatus for reducing power consumption for power supplied by a voltage adapter Grant 6,754,092 - McDowell , et al. June 22, 2	2004-06-22
Method and system for short-circuit current modeling in CMOS integrated circuits App 20040117169 - Acar, Emrah ; et al.	2004-06-17
Apparatus for measuring capacitance of a semiconductor device Grant 6,731,129 - Belluomini , et al. May 4, 2	2004-05-04
Method and system for modeling of effective capacitance in logic circuits App 20040073418 - Nassif, Sani Richard	2004-04-15
Decoupling capacitor sizing and placement App 20040073881 - Nassif, Sani Richard ; et al.	2004-04-15
Method and system for power node current waveform modeling App 20040054974 - Acar, Emrah ; et al.	2004-03-18
Method and apparatus for reducing power consumption for power supplied by a voltage adapter App 20040001346 - McDowell, Chandler Todd ; et al.	2004-01-01
Method and apparatus for characterized parasitic capacitance between integrated-circuit interconnects Grant 5,963,043 - Nassif October 5, 1	1999-10-05

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