Naritake; Isao

Patent Applications and Registrations

Patent applications and USPTO patent grants for Naritake; Isao.The latest application filed is for "one-time programable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof".

Company Profile

0.15.6

Naritake; Isao - Kanagawa JP
Naritake; Isao - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
One-time programmable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof Grant 8,830,719 - Furukawa , et al. September 9, 2	2014-09-09
One-time Programable Cell Circuit, Semiconductor Integrated Circuit Including The Same, And Data Judging Method Thereof App 20130176765 - FURUKAWA; Hiroyuki ; et al.	2013-07-11
One-time programmable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof Grant 8,432,717 - Furukawa , et al. April 30, 2	2013-04-30
Anti-fuse memory cell and semiconductor memory device Grant 8,174,922 - Naritake May 8, 2	2012-05-08
One-time Programable Cell Circuit, Semiconductor Integrated Circuit Including The Same, And Data Judging Method Thereof App 20110080764 - FURUKAWA; Hiroyuki ; et al.	2011-04-07
Anti-fuse memory cell and semiconductor memory device App 20100271897 - Naritake; Isao	2010-10-28
Semiconductor integrated circuit device and substrate bias controlling method Grant 7,532,059 - Naritake May 12, 2	2009-05-12
Semiconductor integrated circuit device and substrate bias controlling method App 20070236277 - Naritake; Isao	2007-10-11
Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other Grant 6,731,547 - Naritake May 4, 2	2004-05-04
Semiconductor memory device Grant 6,601,197 - Naritake July 29, 2	2003-07-29
Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other App 20030117858 - Naritake, Isao	2003-06-26
Semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other App 20020008555 - Naritake, Isao	2002-01-24
Dynamic type semiconductor memory device having function of compensating for threshold value Grant 6,130,845 - Ootsuki , et al. October 10, 2	2000-10-10
Semiconductor memory device having internal timing generator shared between data read/write and burst access Grant 6,038,184 - Naritake March 14, 2	2000-03-14
DRAM having memory cells each using one transfer gate and one capacitor to store plural bit data Grant 5,995,403 - Naritake November 30, 1	1999-11-30
Semiconductor memory device stably storing multiple-valued data without a decrease in operation margin Grant 5,978,255 - Naritake November 2, 1	1999-11-02
Semiconductor memory device including main/sub-bit line arrangement Grant 5,732,026 - Sugibayashi , et al. March 24, 1	1998-03-24
Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern Grant 5,436,910 - Takeshima , et al. July 25, 1	1995-07-25
Double word line type dynamic RAM having redundant sub-array of cells Grant 5,414,660 - Sugibayashi , et al. May 9, 1	1995-05-09
Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed Grant 5,406,526 - Sugibayashi , et al. April 11, 1	1995-04-11

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