loadpatents
name:-0.02843713760376
name:-0.018373966217041
name:-0.0015130043029785
NARAYANASWAMY; Ramesh Patent Filings

NARAYANASWAMY; Ramesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for NARAYANASWAMY; Ramesh.The latest application filed is for "message passing multi processor network for simulation vector processing".

Company Profile
1.14.18
  • NARAYANASWAMY; Ramesh - Palo Alto CA
  • Narayanaswamy; Ramesh - Mountain View CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Message Passing Multi Processor Network For Simulation Vector Processing
App 20220253583 - GANESAN; Subramanian ;   et al.
2022-08-11
Clock Aware Simulation Vector Processor
App 20220198120 - NARAYANASWAMY; Ramesh ;   et al.
2022-06-23
Selective execution for partitioned parallel simulations
Grant 10,853,544 - Narayanaswamy , et al. December 1, 2
2020-12-01
Logic simulation and/or emulation which follows hardware semantics
Grant 10,423,740 - Rabinovitch , et al. Sept
2019-09-24
Selective Execution For Partitioned Parallel Simulations
App 20170185700 - Narayanaswamy; Ramesh ;   et al.
2017-06-29
Retiming a design for efficient parallel simulation
Grant 9,558,306 - Narayanaswamy , et al. January 31, 2
2017-01-31
Quasi-dynamic scheduling and dynamic scheduling for efficient parallel simulation
Grant 9,507,896 - Narayanaswamy , et al. November 29, 2
2016-11-29
Retiming A Design For Efficient Parallel Simulation
App 20130297278 - Narayanaswamy; Ramesh ;   et al.
2013-11-07
Quasi-dynamic Scheduling And Dynamic Scheduling For Efficient Parallel Simulation
App 20130297279 - Narayanaswamy; Ramesh ;   et al.
2013-11-07
Selective Execution For Partitioned Parallel Simulations
App 20130290919 - Narayanaswamy; Ramesh ;   et al.
2013-10-31
Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking means
Grant 8,359,186 - Ganesan , et al. January 22, 2
2013-01-22
Logic Simulation And/or Emulation Which Follows Hardware Semantics
App 20100280814 - Rabinovitch; Alexander ;   et al.
2010-11-04
Scalable system for simulation and emulation of electronic circuits using asymmetrical evaluation and canvassing instruction processors
Grant 7,548,842 - Ganesan , et al. June 16, 2
2009-06-16
Compact processor element for a scalable digital logic verification and emulation system
Grant 7,509,602 - Ganesan , et al. March 24, 2
2009-03-24
Method For Delay Immune And Accelerated Evaluation Of Digital Circuits By Compiling Asynchronous Completion Handshaking Means
App 20070294075 - GANESAN; SUBBU ;   et al.
2007-12-20
A system and method for compiling a description of an electronic circuit to instructions adapted to execute on a plurality of processors
App 20070044079 - GANESAN; SUBBU ;   et al.
2007-02-22
A reconfigurable system for verification of electronic circuits using high-speed serial links to connect asymmetrical evaluation and canvassing instruction processors
App 20060277020 - Ganesan; Subbu ;   et al.
2006-12-07
A compact processor element for a scalable digital logic verification and emulation system
App 20060277234 - Ganesan; Subbu ;   et al.
2006-12-07
A scalable system for simulation and emulation of electronic circuits using asymmetrical evaluation and canvassing instruction processors
App 20060277019 - Ganesan; Subbu ;   et al.
2006-12-07
A system and method for simulation of electronic circuits generating clocks and delaying the execution of instructions in a plurality of processors
App 20060277428 - GANESAN; SUBBU ;   et al.
2006-12-07
Functional verification system
Grant 6,691,287 - Ganesan , et al. February 10, 2
2004-02-10
Tracing the change of state of a signal in a functional verification system
Grant 6,629,297 - Ganesan , et al. September 30, 2
2003-09-30
Run-time controller in a functional verification system
Grant 6,625,786 - Ganesan , et al. September 23, 2
2003-09-23
Functional verification system
App 20030041308 - Ganesan, Subbu ;   et al.
2003-02-27
Functional verification of both cycle-based and non-cycle based designs
Grant 6,480,988 - Ganesan , et al. November 12, 2
2002-11-12
Tracing different states reached by a signal in a functional verification system
Grant 6,470,480 - Ganesan , et al. October 22, 2
2002-10-22
Run-time controller in a functional verification system
App 20020120907 - Ganesan, Subbu ;   et al.
2002-08-29
Tracing different states reached by a signal in a functional verification system
App 20020116689 - Ganesan, Subbu ;   et al.
2002-08-22
Tracing the change of state of a signal in a functional verification system
App 20020116693 - Ganesan, Subbu ;   et al.
2002-08-22
Functional verification of both cycle-based and non-cycle based designs
App 20020112217 - Ganesan, Subbu ;   et al.
2002-08-15

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