Narayanaswami; Ravi
Patent Applications and Registrations
Patent applications and USPTO patent grants for Narayanaswami; Ravi.The latest application filed is for "memory sharing".
Company Profile
29.33.36
- Narayanaswami; Ravi - San Jose CA
- - San Jose CA US
- Narayanaswami; Ravi - Saratoga CA
- Narayanaswami; Ravi - Newark CA
Patent Activity
| Patent | Date |
|---|---|
| Memory Sharing App 20220300421 - Gupta; Suyog ; et al. | 2022-09-22 |
| Neural network compute tile Grant 11,422,801 - Temam , et al. August 23, 2 | 2022-08-23 |
| Redistributing Tensor Elements Between Machine Learning Computing Units App 20220245453 - Majnemer; David Alexander ; et al. | 2022-08-04 |
| Neural network instruction set architecture Grant 11,379,707 - Narayanaswami , et al. July 5, 2 | 2022-07-05 |
| Matrix processing apparatus Grant 11,366,877 - Narayanaswami , et al. June 21, 2 | 2022-06-21 |
| Neural Network Accelerator Tile Architecture With Three-dimensional Stacking App 20220147793 - Nowatzyk; Andreas Georg ; et al. | 2022-05-12 |
| Exploiting Input Data Sparsity In Neural Network Compute Units App 20220083480 - Woo; Dong Hyuk ; et al. | 2022-03-17 |
| Virtualizing External Memory As Local To A Machine Learning Accelerator App 20220044153 - Madar, III; Lawrence J. ; et al. | 2022-02-10 |
| Virtualizing external memory as local to a machine learning accelerator Grant 11,176,493 - Madar, III , et al. November 16, 2 | 2021-11-16 |
| Image transformation for machine learning Grant 11,170,469 - Killebrew , et al. November 9, 2 | 2021-11-09 |
| Hardware Circuit For Accelerating Neural Network Computations App 20210326683 - Narayanaswami; Ravi ; et al. | 2021-10-21 |
| Exploiting input data sparsity in neural network compute units Grant 11,106,606 - Woo , et al. August 31, 2 | 2021-08-31 |
| Hardware double buffering using a special purpose computational unit Grant 11,099,772 - Temam , et al. August 24, 2 | 2021-08-24 |
| Apparatus And Mechanism For Processing Neural Network Tasks Using A Single Chip Package With Multiple Identical Dies App 20210256361 - Dasari; Uday Kumar ; et al. | 2021-08-19 |
| Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies Grant 10,936,942 - Dasari , et al. March 2, 2 | 2021-03-02 |
| Matrix Processing Apparatus App 20210034697 - Narayanaswami; Ravi ; et al. | 2021-02-04 |
| Low-power Adder Circuit App 20210019361 - Kane; Anand Suresh ; et al. | 2021-01-21 |
| Alternative loop limits for accessing data in multi-dimensional tensors Grant 10,885,434 - Temam , et al. January 5, 2 | 2021-01-05 |
| Low-power adder circuit Grant 10,824,692 - Kane , et al. November 3, 2 | 2020-11-03 |
| Virtualizing External Memory As Local To A Machine Learning Accelerator App 20200342350 - Madar, III; Lawrence J. ; et al. | 2020-10-29 |
| Accessing prologue and epilogue data Grant 10,802,956 - Temam , et al. October 13, 2 | 2020-10-13 |
| Matrix processing apparatus Grant 10,719,575 - Narayanaswami , et al. | 2020-07-21 |
| Hardware Double Buffering Using A Special Purpose Computational Unit App 20200183612 - Temam; Olivier ; et al. | 2020-06-11 |
| Low-power Adder Circuit App 20200117696 - Kane; Anand Suresh ; et al. | 2020-04-16 |
| Image Transformation For Machine Learning App 20200027195 - Killebrew; Carrell Daniel ; et al. | 2020-01-23 |
| Multi-input floating-point adder Grant 10,534,578 - Narayanaswami Ja | 2020-01-14 |
| Accessing data in multi-dimensional tensors using adders Grant 10534607 - | 2020-01-14 |
| Exploiting Input Data Sparsity In Neural Network Compute Units App 20200012608 - Woo; Dong Hyuk ; et al. | 2020-01-09 |
| Matrix Processing Apparatus App 20200012705 - Narayanaswami; Ravi ; et al. | 2020-01-09 |
| Neural Network Accelerator With Parameters Resident On Chip App 20200005128 - Temam; Olivier ; et al. | 2020-01-02 |
| Neural network accelerator with parameters resident on chip Grant 10,504,022 - Temam , et al. Dec | 2019-12-10 |
| Hardware double buffering using a special purpose computational unit Grant 10,496,326 - Temam , et al. De | 2019-12-03 |
| Matrix processing apparatus Grant 10,417,303 - Narayanaswami , et al. Sept | 2019-09-17 |
| Image transformation for machine learning Grant 10,373,291 - Killebrew , et al. | 2019-08-06 |
| Image Transformation For Machine Learning App 20190236755 - Killebrew; Carrell Daniel ; et al. | 2019-08-01 |
| Exploiting input data sparsity in neural network compute units Grant 10,360,163 - Woo , et al. | 2019-07-23 |
| Neural Network Compute Tile App 20190213005 - Temam; Olivier ; et al. | 2019-07-11 |
| Alternative Loop Limits For Accessing Data In Multi-dimensional Tensors App 20190205756 - Temam; Olivier ; et al. | 2019-07-04 |
| Apparatus And Mechanism For Processing Neural Network Tasks Using A Single Chip Package With Multiple Identical Dies App 20190156187 - Dasari; Uday Kumar ; et al. | 2019-05-23 |
| Hardware Double Buffering Using A Special Purpose Computational Unit App 20190138243 - Temam; Olivier ; et al. | 2019-05-09 |
| Alternative loop limits for accessing data in multi-dimensional tensors Grant 10,248,908 - Temam , et al. | 2019-04-02 |
| Neural Network Accelerator With Parameters Resident On Chip App 20190050717 - Temam; Olivier ; et al. | 2019-02-14 |
| Accessing Prologue And Epilogue Data App 20190034327 - Temam; Olivier ; et al. | 2019-01-31 |
| Hardware Double Buffering Using A Special Purpose Computational Unit App 20190012112 - Temam; Olivier ; et al. | 2019-01-10 |
| Neural network compute tile Grant 10,175,980 - Temam , et al. J | 2019-01-08 |
| Hardware double buffering using a special purpose computational unit Grant 10,175,912 - Temam , et al. J | 2019-01-08 |
| Alternative Loop Limits App 20180365561 - Temam; Olivier ; et al. | 2018-12-20 |
| Neural Network Accelerator Tile Architecture With Three-dimensional Stacking App 20180365553 - Nowatzyk; Andreas Georg ; et al. | 2018-12-20 |
| Accessing Data In Multi-dimensional Tensors Using Adders App 20180341479 - Temam; Olivier ; et al. | 2018-11-29 |
| Accessing prologue and epilogue data Grant 10,108,538 - Temam , et al. October 23, 2 | 2018-10-23 |
| Neural Network Instruction Set Architecture App 20180197068 - Narayanaswami; Ravi ; et al. | 2018-07-12 |
| Neural Network Compute Tile App 20180121196 - Temam; Olivier ; et al. | 2018-05-03 |
| Exploiting Input Data Sparsity In Neural Network Compute Units App 20180121377 - Woo; Dong Hyuk ; et al. | 2018-05-03 |
| Neural Network Instruction Set Architecture App 20180121786 - Narayanaswami; Ravi ; et al. | 2018-05-03 |
| Neural network instruction set architecture Grant 9,959,498 - Narayanaswami , et al. May 1, 2 | 2018-05-01 |
| Accessing data in multi-dimensional tensors using adders Grant 9,946,539 - Temam , et al. April 17, 2 | 2018-04-17 |
| Neural network accelerator tile architecture with three-dimensional stacking Grant 9,928,460 - Nowatzyk , et al. March 27, 2 | 2018-03-27 |
| Matrix Processing Apparatus App 20180060276 - Narayanaswami; Ravi ; et al. | 2018-03-01 |
| Matrix processing apparatus Grant 9,898,441 - Narayanaswami , et al. February 20, 2 | 2018-02-20 |
| Matrix processing apparatus Grant 9,880,976 - Narayanaswami , et al. January 30, 2 | 2018-01-30 |
| Neural network instruction set architecture Grant 9,836,691 - Narayanaswami , et al. December 5, 2 | 2017-12-05 |
| Exploiting input data sparsity in neural network compute units Grant 9,818,059 - Woo , et al. November 14, 2 | 2017-11-14 |
| Matrix processing apparatus Grant 9,805,001 - Narayanaswami , et al. October 31, 2 | 2017-10-31 |
| Matrix processing apparatus Grant 9,798,701 - Narayanaswami , et al. October 24, 2 | 2017-10-24 |
| Matrix Processing Apparatus App 20170228344 - Narayanaswami; Ravi ; et al. | 2017-08-10 |
| Matrix Processing Apparatus App 20170228341 - Narayanaswami; Ravi ; et al. | 2017-08-10 |
| Matrix Processing Apparatus App 20170228342 - Narayanaswami; Ravi ; et al. | 2017-08-10 |
| Matrix Processing Apparatus App 20170228343 - Narayanaswami; Ravi ; et al. | 2017-08-10 |
| Neural network compute tile Grant 9,710,265 - Temam , et al. July 18, 2 | 2017-07-18 |
| Semiconductor multi-device system with logic means for controlling the operational mode of a set of input/output data bus drivers Grant 5,287,464 - Kumar , et al. February 15, 1 | 1994-02-15 |
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