Narayan; Rani R.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Narayan; Rani R..The latest application filed is for "integrated circuit selective scaling".
- Narayan; Rani R. - San Jose CA
| Patent | Date |
|---|---|
| Integrated circuit selective scaling Grant 7,882,463 - Heng , et al. February 1, 2 | 2011-02-01 |
| Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs Grant 7,484,197 - Allen , et al. January 27, 2 | 2009-01-27 |
| Integrated Circuit Selective Scaling App 20080148210 - Heng; Fook-Luen ; et al. | 2008-06-19 |
| Integrated circuit selective scaling Grant 7,363,601 - Heng , et al. April 22, 2 | 2008-04-22 |
| Minimum Layout Perturbation-based Artwork Legalization With Grid Constraints For Hierarchical Designs App 20070245283 - Allen; RobertJ ; et al. | 2007-10-18 |
| Integrated Circuit Selective Scaling App 20060085768 - Heng; Fook-Luen ; et al. | 2006-04-20 |
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