Narayan; Chandrasekhar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Narayan; Chandrasekhar.The latest application filed is for "cognitive horizon surveillance".

Company Profile

0.57.33

Narayan; Chandrasekhar - San Jose CA
Narayan; Chandrasekhar - Hopewell Junction NY
Narayan; Chandrasekhar - Dutchess County NY
Narayan; Chandrasekhar - Beacon NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Cognitive Horizon Surveillance App 20210406314 - Gruhl; Daniel ; et al.	2021-12-30
Expert-in-the-loop Ai For Materials Generation App 20210304852 - Ristoski; Petar ; et al.	2021-09-30
Expert-in-the-loop Ai For Materials Discovery App 20210303762 - Ristoski; Petar ; et al.	2021-09-30
Damage-free self-limiting through-substrate laser ablation Grant 10,486,268 - Doany , et al. Nov	2019-11-26
Damage-free Self-limiting Through-substrate Laser Ablation App 20170157712 - Doany; Fuad E. ; et al.	2017-06-08
Carbon nanotube device Grant 9,640,765 - Clevenger , et al. May 2, 2	2017-05-02
Damage-free self-limiting through-substrate laser ablation Grant 9,576,836 - Doany , et al. February 21, 2	2017-02-21
Carbon Nanotube Device App 20160336515 - Clevenger; Lawrence A. ; et al.	2016-11-17
Carbon nanotube device Grant 9,406,888 - Clevenger , et al. August 2, 2	2016-08-02
Damage-free Self-limiting Through-substrate Laser Ablation App 20160133468 - Doany; Fuad E. ; et al.	2016-05-12
Reprogrammable electrical fuse Grant 9,058,887 - Hsu , et al. June 16, 2	2015-06-16
Carbon Nanotube Device App 20150041763 - Clevenger; Lawrence A. ; et al.	2015-02-12
Structure and method for integrated synaptic element Grant 8,829,986 - Clevenger , et al. September 9, 2	2014-09-09
Electronic synapse Grant 8,463,723 - Modha , et al. June 11, 2	2013-06-11
Recording head with tilted orientation Grant 8,416,537 - Berman , et al. April 9, 2	2013-04-09
Recording Head With Tilted Orientation App 20110109998 - Berman; David ; et al.	2011-05-12
Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer Grant 7,804,148 - Hsu , et al. September 28, 2	2010-09-28
Electronic Synapse App 20100223220 - Modha; Dharmendra S. ; et al.	2010-09-02
Chip and wafer integration process using vertical connections Grant 7,564,118 - Pogge , et al. July 21, 2	2009-07-21
Seedless wirebond pad plating Grant 7,534,651 - Narayan , et al. May 19, 2	2009-05-19
Reprogrammable Electrical Fuse App 20090109722 - Hsu; Louis C. ; et al.	2009-04-30
Waveguide polarization beam splitters and method of fabricating a waveguide wire-grid polarization beam splitter Grant 7,486,845 - Black , et al. February 3, 2	2009-02-03
Chip And Wafer Integration Process Using Vertical Connections App 20080230891 - Pogge; H. Bernhard ; et al.	2008-09-25
Waveguide Polarization Beam Splitters And Method Of Fabricating A Waveguide Wire-grid Polarization Beam Splitter App 20080175527 - Black; Charles T. ; et al.	2008-07-24
Chip and wafer integration process using vertical connections Grant 7,388,277 - Pogge , et al. June 17, 2	2008-06-17
Reprogrammable electrical fuse Grant 7,298,639 - Hsu , et al. November 20, 2	2007-11-20
Waveguide polarization beam splitters and method of fabricating a waveguide wire-grid polarization beam splitter Grant 7,298,935 - Black , et al. November 20, 2	2007-11-20
Waveguide Polarization Beam Splitters And Method Of Fabricating A Waveguide Wire-grid Polarization Beam Splitter App 20070253661 - Black; Charles T. ; et al.	2007-11-01
Opto-thermal annealing mask and method App 20070187670 - Hsu; Louis L. ; et al.	2007-08-16
Seedless wirebond pad plating App 20070007659 - Narayan; Chandrasekhar ; et al.	2007-01-11
Line level air gaps App 20060264036 - Chen; Shyng-Tsong ; et al.	2006-11-23
Reprogrammable Electrical Fuse App 20060249808 - Hsu; Louis C. ; et al.	2006-11-09
Seedless wirebond pad plating Grant 7,115,997 - Narayan , et al. October 3, 2	2006-10-03
Line level air gaps Grant 7,084,479 - Chen , et al. August 1, 2	2006-08-01
Copper recess process with application to selective capping and electroless plating Grant 7,064,064 - Chen , et al. June 20, 2	2006-06-20
High density chip carrier with integrated passive devices Grant 7,030,481 - Chudzik , et al. April 18, 2	2006-04-18
Copper recess process with application to selective capping and electroless plating Grant 6,975,032 - Chen , et al. December 13, 2	2005-12-13
High density chip carrier with integrated passive devices Grant 6,962,872 - Chudzik , et al. November 8, 2	2005-11-08
Fuse structure and method to form the same Grant 6,927,472 - Anderson , et al. August 9, 2	2005-08-09
Fuse structure and method to form the same Grant 6,924,185 - Anderson , et al. August 2, 2	2005-08-02
Copper recess process with application to selective capping and electroless plating App 20050158985 - Chen, Shyng-Tsong ; et al.	2005-07-21
Line level air gaps App 20050127514 - Chen, Shyng-Tsong ; et al.	2005-06-16
Chip and wafer integration process using vertical connections App 20050121711 - Pogge, H. Bernhard ; et al.	2005-06-09
Seedless Wirebond Pad Plating App 20050104217 - Narayan, Chandrasekhar ; et al.	2005-05-19
Chip and wafer integration process using vertical connections Grant 6,856,025 - Pogge , et al. February 15, 2	2005-02-15
High density chip carrier with integrated passive devices App 20050023664 - Chudzik, Michael Patrick ; et al.	2005-02-03
Structure and method for reducing thermo-mechanical stress in stacked vias Grant 6,831,363 - Dalton , et al. December 14, 2	2004-12-14
Copper recess process with application to selective capping and electroless plating App 20040113279 - Chen, Shyng-Tsong ; et al.	2004-06-17
Structure and method for reducing thermo-mechanical stress in stacked vias App 20040113278 - Dalton, Timothy J. ; et al.	2004-06-17
High density chip carrier with integrated passive devices App 20040108587 - Chudzik, Michael Patrick ; et al.	2004-06-10
Fuse structure and method to form the same App 20040070049 - Anderson, David K. ; et al.	2004-04-15
Variable resistor structure and method for forming and programming a variable resistor for electronic circuits Grant 6,700,161 - Hsu , et al. March 2, 2	2004-03-02
TFT LCD active data line repair Grant 6,697,037 - Alt , et al. February 24, 2	2004-02-24
Variable resistor structure and method for forming and programming a variable resistor for electronic circuits App 20030213998 - Hsu, Louis Lu-Chen ; et al.	2003-11-20
Chip and wafer integration process using vertical connections App 20030215984 - Pogge, H. Bernhard ; et al.	2003-11-20
System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient Grant 6,624,499 - Kothandaraman , et al. September 23, 2	2003-09-23
System For Programming Fuse Structure By Electromigration Of Silicide Enhanced By Creating Temperature Gradient App 20030160297 - Kothandaraman, Chandrasekharan ; et al.	2003-08-28
Chip and wafer integration process using vertical connections Grant 6,599,778 - Pogge , et al. July 29, 2	2003-07-29
Chip And Wafer Integration Process Using Vertical Connections App 20030111733 - Pogge, H. Bernhard ; et al.	2003-06-19
Metal wire fuse structure with cavity Grant 6,566,238 - Brintzinger , et al. May 20, 2	2003-05-20
Fuse structure and method to form the same App 20030089962 - Anderson, David K. ; et al.	2003-05-15
Method of using optical proximity effects to create electrically blown fuses with sub-critical dimension neck downs Grant 6,436,585 - Narayan , et al. August 20, 2	2002-08-20
Multi-level fuse structure App 20020100956 - Brintzinger, Axel Christoph ; et al.	2002-08-01
Fuse processing using dielectric planarization pillars Grant 6,420,216 - Clevenger , et al. July 16, 2	2002-07-16
Electrical fuses employing reverse biasing to enhance programming Grant 6,323,535 - Iyer , et al. November 27, 2	2001-11-27
Metal wire fuse structure with cavity App 20010020728 - Brintzinger, Axel C. ; et al.	2001-09-13
Mixed fuse technologies Grant 6,288,436 - Narayan , et al. September 11, 2	2001-09-11
Manufacturing of cavity fuses on gate conductor level Grant 6,274,440 - Arndt , et al. August 14, 2	2001-08-14
Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells Grant 6,266,272 - Kirihata , et al. July 24, 2	2001-07-24
Vertical fuse and method of fabrication Grant 6,242,789 - Weber , et al. June 5, 2	2001-06-05
Vertical fuse and method of fabrication Grant 6,218,279 - Weber , et al. April 17, 2	2001-04-17
Defect management engine for semiconductor memories and memory systems Grant 6,141,267 - Kirihata , et al. October 31, 2	2000-10-31
Soft passivation layer in semiconductor fabrication Grant 6,127,721 - Narayan , et al. October 3, 2	2000-10-03
Conductor-insulator-conductor structure Grant 6,081,021 - Gambino , et al. June 27, 2	2000-06-27
Micro-scale part positioning by surface interlocking Grant 6,029,881 - Chalco , et al. February 29, 2	2000-02-29
X-ray mask pellicle Grant 5,793,836 - Maldonado , et al. August 11, 1	1998-08-11
Mechanical packaging and thermal management of flat mirror arrays Grant 5,764,314 - Narayan , et al. June 9, 1	1998-06-09
Thermoformed three dimensional wiring module Grant 5,659,153 - Narayan , et al. August 19, 1	1997-08-19
Flat panel display containing black matrix polymer Grant 5,619,357 - Angelopoulos , et al. April 8, 1	1997-04-08
Device to monitor and control the temperature of electronic chips to enhance reliability Grant 5,569,950 - Lewis , et al. October 29, 1	1996-10-29
Method for fabricating multi-layer thin film structure having a separation layer Grant 5,534,094 - Arjavalingam , et al. July 9, 1	1996-07-09
Electronic structures having a joining geometry providing reduced capacitive loading Grant 5,471,090 - Deutsch , et al. November 28, 1	1995-11-28
Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal Grant 5,420,073 - DiGiacomo , et al. May 30, 1	1995-05-30
Sealed DASD having humidity control and method of making same Grant 5,392,177 - Chainer , et al. February 21, 1	1995-02-21
Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal Grant 5,367,195 - DiGiacomo , et al. November 22, 1	1994-11-22
Multi-layer thin film structure and parallel processing method for fabricating same Grant 5,258,236 - Arjavalingam , et al. November 2, 1	1993-11-02
Multilayered metallurgical structure for an electronic component Grant 4,985,310 - Agarwala , et al. January 15, 1	1991-01-15