Nanjundiah; Bhavani Shringari

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nanjundiah; Bhavani Shringari.The latest application filed is for "system and method for pseudo-random test pattern memory allocation for processor design verification and validation".

Company Profile

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Nanjundiah; Bhavani Shringari - Bangalore IN
Nanjundiah; Bhavani Shringari - Karnataka IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode Grant 8,127,192 - Arora , et al. February 28, 2	2012-02-28
System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation Grant 7,689,886 - Arora , et al. March 30, 2	2010-03-30
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation Grant 7,647,539 - Bussa , et al. January 12, 2	2010-01-12
System and method for pseudo-random test pattern memory allocation for processor design verification and validation Grant 7,584,394 - Choudhury , et al. September 1, 2	2009-09-01
System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation App 20090024892 - Bussa; Vinod ; et al.	2009-01-22
System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation App 20090024886 - Arora; Sampan ; et al.	2009-01-22
System And Method For Predicting Iwarx And Stwcx Instructions In Test Pattern Generation And Simulation For Processor Design Verification/validation In Interrupt Mode App 20090024894 - Arora; Sampan ; et al.	2009-01-22
System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation App 20090024891 - Choudhury; Shubhodeep Roy ; et al.	2009-01-22

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