loadpatents
Patent applications and USPTO patent grants for Namishia; Daniel.The latest application filed is for "methods for pillar connection on frontside and passive device integration on backside of die".
Patent | Date |
---|---|
Methods For Pillar Connection On Frontside And Passive Device Integration On Backside Of Die App 20220208758 - Alcorn; Terry ;   et al. | 2022-06-30 |
Methods For Pillar Connection On Frontside And Passive Device Integration On Backside Of Die App 20210375856 - Alcorn; Terry ;   et al. | 2021-12-02 |
Semiconductor Die With Improved Ruggedness App 20210043530 - Hardiman; Chris ;   et al. | 2021-02-11 |
Semiconductor die with improved ruggedness Grant 10,886,189 - Hardiman , et al. January 5, 2 | 2021-01-05 |
Semiconductor die with improved ruggedness Grant 10,840,162 - Hardiman , et al. November 17, 2 | 2020-11-17 |
Semiconductor Die With Improved Ruggedness App 20190259682 - Hardiman; Chris ;   et al. | 2019-08-22 |
Semiconductor die with improved ruggedness Grant 10,332,817 - Hardiman , et al. | 2019-06-25 |
Semiconductor Die With Improved Ruggedness App 20190172769 - Hardiman; Chris ;   et al. | 2019-06-06 |
Floating bond pad for power semiconductor devices Grant 10,068,834 - Haney , et al. September 4, 2 | 2018-09-04 |
Stress mitigation for thin and thick films used in semiconductor circuitry Grant 9,934,983 - Ring , et al. April 3, 2 | 2018-04-03 |
Encapsulation of advanced devices using novel PECVD and ALD schemes Grant 9,812,338 - Ring , et al. November 7, 2 | 2017-11-07 |
PECVD protective layers for semiconductor devices Grant 9,761,439 - Ring , et al. September 12, 2 | 2017-09-12 |
Pecvd Protective Layers For Semiconductor Devices App 20160172315 - Ring; Zoltan ;   et al. | 2016-06-16 |
Using stress reduction barrier sub-layers in a semiconductor die Grant 9,269,662 - Ring , et al. February 23, 2 | 2016-02-23 |
Ohmic contact to semiconductor device Grant 9,214,352 - Hagleitner , et al. December 15, 2 | 2015-12-15 |
Ni-rich Schottky contact Grant 9,202,703 - Hagleitner , et al. December 1, 2 | 2015-12-01 |
Stress Mitigation For Thin And Thick Films Used In Semiconductor Circuitry App 20150221574 - Ring; Zoltan ;   et al. | 2015-08-06 |
Encapsulation Of Advanced Devices Using Novel Pecvd And Ald Schemes App 20140264960 - Ring; Zoltan ;   et al. | 2014-09-18 |
Floating Bond Pad For Power Semiconductor Devices App 20140246790 - Haney; Sarah Kay ;   et al. | 2014-09-04 |
Ni-rich Schottky Contact App 20140124792 - Hagleitner; Helmut ;   et al. | 2014-05-08 |
Using Stress Reduction Barrier Sub-layers In A Semiconductor Die App 20140103363 - Ring; Zoltan ;   et al. | 2014-04-17 |
Ohmic Contact To Semiconductor Device App 20120175682 - Hagleitner; Helmut ;   et al. | 2012-07-12 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.