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name:-0.0093479156494141
name:-0.019289016723633
name:-0.00049304962158203
Nakazato; Shinji Patent Filings

Nakazato; Shinji

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nakazato; Shinji.The latest application filed is for "semiconductor integrated circuit device".

Company Profile
0.15.6
  • Nakazato; Shinji - Maebashi JP
  • Nakazato; Shinji - Takasaki JP
  • Nakazato, Shinji - Takasaki-shi JP
  • Nakazato; Shinji - Koganei JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor integrated circuit device
Grant 7,982,314 - Shinozaki , et al. July 19, 2
2011-07-19
Semiconductor integrated circuit device
App 20100308458 - Shinozaki; Masao ;   et al.
2010-12-09
Semiconductor integrated circuit device
Grant 7,808,107 - Shinozaki , et al. October 5, 2
2010-10-05
Semiconductor integrated circuit device
App 20090219069 - Shinozaki; Masao ;   et al.
2009-09-03
Semiconductor integrated circuit device
Grant 7,547,971 - Shinozaki , et al. June 16, 2
2009-06-16
Semiconductor integrated circuit device
App 20060006480 - Shinozaki; Masao ;   et al.
2006-01-12
Semiconductor integrated circuit device
Grant 6,963,136 - Shinozaki , et al. November 8, 2
2005-11-08
Semiconductor memory device
Grant 6,864,559 - Nakazato , et al. March 8, 2
2005-03-08
Semiconductor memory device
Grant 6,740,958 - Nakazato , et al. May 25, 2
2004-05-25
Semiconductor integrated circuit device
App 20040007778 - Shinozaki, Masao ;   et al.
2004-01-15
Semiconductor memory device
App 20030178699 - Nakazato, Shinji ;   et al.
2003-09-25
Semiconductor memory device
App 20020153591 - Nakazato, Shinji ;   et al.
2002-10-24
Semiconductor memory device
Grant 6,208,010 - Nakazato , et al. March 27, 2
2001-03-27
Semiconductor device
Grant 5,638,335 - Akiyama , et al. June 10, 1
1997-06-10
Semiconductor memory device having separately biased wells for isolation
Grant 5,497,023 - Nakazato , et al. March 5, 1
1996-03-05
Semiconductor CMOS memory device with separately biased wells
Grant 5,386,135 - Nakazato , et al. January 31, 1
1995-01-31
Semiconductor memory device having bipolar transistor and structure to avoid soft error
Grant 5,324,982 - Nakazato , et al. June 28, 1
1994-06-28
Semiconductor memory device
Grant 5,148,255 - Nakazato , et al. September 15, 1
1992-09-15
Memory device with improved common data line bias arrangement
Grant 5,050,127 - Mitsumoto , et al. * September 17, 1
1991-09-17
Semiconductor device
Grant 4,868,626 - Nakazato , et al. * September 19, 1
1989-09-19
Memory device with improved common data line bias arrangement
Grant 4,829,479 - Mitsumoto , et al. May 9, 1
1989-05-09

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