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Patent applications and USPTO patent grants for Nakanishi, Chikako.The latest application filed is for "arithmetic unit comprising a memory shared by a plurality of processors".
Patent | Date |
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Arithmetic unit comprising a memory shared by a plurality of processors App 20020095562 - Nakanishi, Chikako ;   et al. | 2002-07-18 |
Instruction cache memory apparatus with advanced read function that predicts whether to read out a next instruction block including an address register, a counter and a selector Grant 5,940,857 - Nakanishi , et al. August 17, 1 | 1999-08-17 |
Branch prediction system for superscalar processor Grant 5,835,754 - Nakanishi November 10, 1 | 1998-11-10 |
Parallel processor performing bypass control by grasping portions in which instructions exist Grant 5,805,852 - Nakanishi September 8, 1 | 1998-09-08 |
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