Nakamae; Masahiko

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nakamae; Masahiko.The latest application filed is for "method of producing strained si-soi substrate and strained si-soi substrate produced by the same".

Company Profile

0.9.4

Nakamae; Masahiko - Tokyo JP
Nakamae; Masahiko - Saga JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same Grant 7,977,221 - Ninomiya , et al. July 12, 2	2011-07-12
Method for manufacturing semiconductor wafer including a strained silicon layer Grant 7,767,548 - Ninomiya , et al. August 3, 2	2010-08-03
METHOD OF PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THE SAME App 20090090933 - Ninomiya; Masaharu ; et al.	2009-04-09
Method for Manufacturing Semiconductor Wafer App 20090047526 - Ninomiya; Masaharu ; et al.	2009-02-19
Pasted SOI substrate, process for producing the same and semiconductor device Grant 7,253,082 - Adachi , et al. August 7, 2	2007-08-07
Production method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by same App 20060214257 - Ninomiya; Masaharu ; et al.	2006-09-28
Pasted soi substrate, process for producing the same and semiconductor device App 20050081958 - Adachi, Naoshi ; et al.	2005-04-21
Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film, and a method for manufacturing the semiconductor device Grant 6,372,628 - Matsubara , et al. April 16, 2	2002-04-16
Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film Grant 6,091,081 - Matsubara , et al. July 18, 2	2000-07-18
Method of manufacturing a bipolar transistor having thin base region Grant 5,296,391 - Sato , et al. March 22, 1	1994-03-22
Semiconductor device having bipolar transistor with trench Grant 4,963,957 - Ohi , et al. October 16, 1	1990-10-16
Semiconductor device having multilayer silicide contact system and process of fabrication thereof Grant 4,800,177 - Nakamae January 24, 1	1989-01-24
Method of manufacturing PN junctions in a semiconductor region to reach an isolation layer without exposing the semiconductor region surface Grant 4,191,595 - Aomura , et al. March 4, 1	1980-03-04

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