Naini; Ajay

Patent Applications and Registrations

Patent applications and USPTO patent grants for Naini; Ajay.The latest application filed is for "error detection in dynamic logic circuits".

Company Profile

0.6.3

Naini; Ajay - Saratoga CA
Naini; Ajay - San Jose CA
Naini; Ajay - Plano TX
Naini; Ajay - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Core redundancy in a chip multiprocessor for highly reliable systems Grant 7,328,371 - Kalyanasundharam , et al. February 5, 2	2008-02-05
Error detection in dynamic logic circuits Grant 6,954,912 - Srivastava , et al. October 11, 2	2005-10-11
Error detection in dynamic logic circuits App 20030217307 - Srivastava, Pranjal ; et al.	2003-11-20
Method and apparatus for reduction of noise sensitivity in dynamic logic circuits Grant 6,603,333 - Vinh , et al. August 5, 2	2003-08-05
Elimination of rounding step in the short path of a floating point adder App 20030115236 - Naini, Ajay ; et al.	2003-06-19
Read Port Design And Method For Register Array App 20030058718 - Kalyanasundharam, Vydhyanathan ; et al.	2003-03-27
Converting biased exponents from single/double precision to extended precision without requiring an adder Grant 5,523,961 - Naini June 4, 1	1996-06-04
Method and apparatus for performing carry look-ahead addition in a data processor Grant 5,276,635 - Naini , et al. January 4, 1	1994-01-04
Recoded iterative multiplier Grant 5,220,525 - Anderson , et al. June 15, 1	1993-06-15

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