| Patent | Date |
|---|
Cross-coupled transistor threshold voltage mismatch compensation and related devices, systems, and methods
Grant 11,289,151 - Nagata March 29, 2 | 2022-03-29 |
Sense amplifier schemes for accessing memory cells
Grant 11,270,740 - Nagata March 8, 2 | 2022-03-08 |
Cross-coupled Transistor Threshold Voltage Mismatch Compensation And Related Devices, Systems, And Methods
App 20210142842 - Nagata; Kyoichi | 2021-05-13 |
Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
Grant 10,916,289 - Nagata February 9, 2 | 2021-02-09 |
Sense Amplifier Schemes For Accessing Memory Cells
App 20190385650 - Nagata; Kyoichi | 2019-12-19 |
Apparatuses And Methods Including Ferroelectric Memory And For Accessing Ferroelectric Memory
App 20190371385 - Nagata; Kyoichi | 2019-12-05 |
Semiconductor device
Grant 10,490,260 - Nagata , et al. Nov | 2019-11-26 |
Apparatuses and methods for accessing ferroelectric memory including providing reference voltage level
Grant 10,403,347 - Nagata Sep | 2019-09-03 |
Sense amplifier schemes for accessing memory cells
Grant 10,388,335 - Nagata A | 2019-08-20 |
Apparatuses And Methods For Accessing Ferroelectric Memory Including Providing Reference Voltage Level
App 20190237122 - Nagata; Kyoichi | 2019-08-01 |
Sense Amplifier Schemes For Accessing Memory Cells
App 20190051335 - Nagata; Kyoichi | 2019-02-14 |
Semiconductor Device
App 20180061480 - Nagata; Kyoichi ; et al. | 2018-03-01 |
Apparatus and method of pre-charge and equalization control for dynamic random access memory
Grant 9,837,139 - Nagata , et al. December 5, 2 | 2017-12-05 |
Semiconductor device having hierarchical sense amplifiers assigned to multiple local bit lines
Grant 9,520,177 - Matsumoto , et al. December 13, 2 | 2016-12-13 |
Apparatuses and methods for charge sharing across data buses based on respective levels of a data buses
Grant 9,424,222 - Nagata August 23, 2 | 2016-08-23 |
Semiconductor Device
App 20150302914 - Matsumoto; Yasuhiro ; et al. | 2015-10-22 |
Semiconductor device having hierarchical bit line structure
Grant 9,159,401 - Nagata October 13, 2 | 2015-10-13 |
Semiconductor device
Grant 9,036,448 - Nagata May 19, 2 | 2015-05-19 |
Semiconductor Device Having Hierarchical Bit Line Structure
App 20150124522 - NAGATA; Kyoichi | 2015-05-07 |
Semiconductor device having hierarchical bit line structure
Grant 8,964,439 - Nagata February 24, 2 | 2015-02-24 |
Semiconductor Device, Control Method Thereof And Data Processing System
App 20140328133 - NAGATA; Kyoichi | 2014-11-06 |
Semiconductor device, control method thereof and data processing system
Grant 8,804,395 - Nagata August 12, 2 | 2014-08-12 |
Semiconductor Device
App 20140211545 - NAGATA; Kyoichi ; et al. | 2014-07-31 |
Semiconductor Device, Control Method Thereof And Data Processing System
App 20140119143 - NAGATA; Kyoichi | 2014-05-01 |
Semiconductor device, control method thereof and data processing system
Grant 8,670,284 - Nagata March 11, 2 | 2014-03-11 |
Semiconductor Device Having Bit Line Hierarchically Structured
App 20130294137 - MOCHIDA; Noriaki ; et al. | 2013-11-07 |
Semiconductor Device Having Hierarchical Bit Line Structure
App 20130215698 - NAGATA; Kyoichi | 2013-08-22 |
Semiconductor Device, Control Method Thereof And Data Processing System
App 20120250437 - NAGATA; Kyoichi | 2012-10-04 |
Semiconductor Device
App 20120230144 - NAGATA; Kyoichi | 2012-09-13 |
Semiconductor memory device that can relief defective address
Grant 8,208,324 - Mochida , et al. June 26, 2 | 2012-06-26 |
Semiconductor device having delay control circuit
Grant 8,134,877 - Nagata March 13, 2 | 2012-03-13 |
Semiconductor device
Grant 7,875,986 - Isa , et al. January 25, 2 | 2011-01-25 |
Semiconductor Device That Supresses Malfunctions Due To Voltage Reduction
App 20100188878 - TAKEDA; Hiromasa ; et al. | 2010-07-29 |
Semiconductor memory device that can relief defective address
App 20100149894 - Mochida; Noriaki ; et al. | 2010-06-17 |
Semiconductor device having delay control circuit
App 20100085824 - Nagata; Kyoichi | 2010-04-08 |
Semiconductor device with a logic circuit
Grant 7,663,411 - Nagata February 16, 2 | 2010-02-16 |
Level-conversion circuit
Grant 7,576,566 - Nagata August 18, 2 | 2009-08-18 |
Semiconductor device with a logic circuit
App 20080258774 - Nagata; Kyoichi | 2008-10-23 |
Semiconductor memory device
Grant 7,436,720 - Nobutoki , et al. October 14, 2 | 2008-10-14 |
Logic gate with reduced sub-threshold leak current
Grant 7,394,297 - Nagata July 1, 2 | 2008-07-01 |
Semiconductor device
App 20080012107 - Isa; Satoshi ; et al. | 2008-01-17 |
Level conversion circuit
App 20080001628 - Nagata; Kyoichi | 2008-01-03 |
Level-conversion Circuit
App 20070296482 - NAGATA; Kyoichi | 2007-12-27 |
Level-conversion circuit
Grant 7,288,963 - Nagata October 30, 2 | 2007-10-30 |
Semiconductor memory device
App 20070127301 - Nobutoki; Tomoko ; et al. | 2007-06-07 |
Logic gate with reduced sub-threshold leak current
App 20060232305 - Nagata; Kyoichi | 2006-10-19 |
Level-conversion circuit
App 20050212557 - Nagata, Kyoichi | 2005-09-29 |
Data latch circuit and driving method thereof
Grant 6,661,270 - Nagata December 9, 2 | 2003-12-09 |
Data latch circuit and driving method thereof
App 20010006350 - Nagata, Kyoichi | 2001-07-05 |
Semiconductor memory device capable of securing large latch margin
Grant 6,229,757 - Nagata , et al. May 8, 2 | 2001-05-08 |
Interface circuit and method of setting determination level therefor
Grant 6,177,816 - Nagata January 23, 2 | 2001-01-23 |
Semiconductor integrated circuit device having clamp circuit for accelerating data transfer on data bus
Grant 6,061,275 - Nagata May 9, 2 | 2000-05-09 |
Semiconductor memory device having dynamic data amplifier circuit capable of reducing power dissipation
Grant 6,009,020 - Nagata December 28, 1 | 1999-12-28 |
Dynamic random access memory device
Grant 5,793,664 - Nagata , et al. August 11, 1 | 1998-08-11 |
Dynamic semiconductor memory circuit
Grant 5,432,744 - Nagata July 11, 1 | 1995-07-11 |
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