NAGARANDAL; Ajay
Patent Applications and Registrations
Patent applications and USPTO patent grants for NAGARANDAL; Ajay.The latest application filed is for "high-speed functional protocol based test and debug".
- NAGARANDAL; Ajay - Dublin CA
- Nagarandal; Ajay - Fremont CA
- Nagarandal; Ajay - San Jose CA
- Nagarandal; Ajay - Sunnyvale CA
| Patent | Date |
|---|---|
| High-speed Functional Protocol Based Test And Debug App 20220120811 - SINHA; Anubhav ; et al. | 2022-04-21 |
| Constraint based bit-stream compression in hardware for programmable devices Grant 10,152,566 - Nagarandal , et al. Dec | 2018-12-11 |
| Behavioral simulation model for clock-data recovery phase-locked loop Grant 9,898,561 - Zhou , et al. February 20, 2 | 2018-02-20 |
| Behavioral Simulation Model For Clock-data Recovery Phase-locked Loop App 20160350455 - Zhou; Bo ; et al. | 2016-12-01 |
| Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks Grant 7,539,957 - Nagarandal May 26, 2 | 2009-05-26 |
| Techniques for automatically generating tests for programmable circuits Grant 7,024,327 - Dastidar , et al. April 4, 2 | 2006-04-04 |
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