Naem; Abdalla Aly

Patent Applications and Registrations

Patent applications and USPTO patent grants for Naem; Abdalla Aly.The latest application filed is for "method of forming a copper topped interconnect structure that has thin and thick copper traces".

Company Profile

0.19.3

Naem; Abdalla Aly - San Jose CA
Naem; Abdalla Aly - Overijse BE
Naem; Abdalla Aly - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming a copper topped interconnect structure that has thin and thick copper traces Grant 8,324,097 - Naem December 4, 2	2012-12-04
Method of forming a copper-compatible fuse target Grant 8,273,608 - Naem September 25, 2	2012-09-25
Copper-compatible fuse target Grant 8,030,733 - Naem October 4, 2	2011-10-04
Fuse target and method of forming the fuse target in a copper process flow Grant 7,964,934 - Naem , et al. June 21, 2	2011-06-21
Stacked die structure with an underlying copper-topped die Grant 7,847,385 - Naem December 7, 2	2010-12-07
Method of Forming a Copper Topped Interconnect Structure that has Thin and Thick Copper Traces App 20100190332 - Naem; Abdalla Aly	2010-07-29
Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure Grant 7,709,956 - Naem , et al. May 4, 2	2010-05-04
Copper-topped Interconnect Structure That Has Thin And Thick Copper Traces And Method Of Forming The Copper-topped Interconnect Structure App 20100065964 - Naem; Abdalla Aly ; et al.	2010-03-18
Method of forming a transistor with a channel region in a layer of composite material Grant 7,118,973 - Naem October 10, 2	2006-10-10
Dual-sided semiconductor device with a resistive element that requires little silicon surface area Grant 7,115,973 - Naem October 3, 2	2006-10-03
Method of forming a MOS transistor with a layer of silicon germanium carbon Grant 7,098,095 - Naem , et al. August 29, 2	2006-08-29
Bipolar transistor with an ultra small self-aligned polysilicon emitter Grant 7,087,979 - Naem August 8, 2	2006-08-08
Bipolar transistor structure with ultra small polysilicon emitter Grant 6,853,017 - Naem February 8, 2	2005-02-08
MOS transistor and method of forming the transistor with a channel region in a layer of composite material Grant 6,818,938 - Naem November 16, 2	2004-11-16
Dual-sided semiconductor device and method of forming the device with a resistive element that requires little silicon surface area Grant 6,784,099 - Naem August 31, 2	2004-08-31
Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor Grant 6,784,065 - Naem August 31, 2	2004-08-31
Method of forming the silicon germanium base of a bipolar transistor Grant 6,753,234 - Naem June 22, 2	2004-06-22
Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor Grant 6,649,482 - Naem November 18, 2	2003-11-18
Bipolar transistor with ultra small polysilicon emitter and method of fabricating the transistor App 20020192916 - Naem, Abdalla Aly	2002-12-19
Method of fabricating a contact structure for an MOS transistor entirely on isolation oxide Grant 5,866,459 - Naem , et al. February 2, 1	1999-02-02
Self-aligned MOSFET gate/source/drain salicide formation Grant 5,780,349 - Naem July 14, 1	1998-07-14
Method of fabricating a raised source/drain MOSFET using self-aligned POCl.sub.3 for doping gate/source/drain regions Grant 5,736,419 - Naem April 7, 1	1998-04-07

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