Nadeau-Dostie; Benoit

Patent Applications and Registrations

Patent applications and USPTO patent grants for Nadeau-Dostie; Benoit.The latest application filed is for "method and apparatus for processing memory repair information".

Company Profile

0.41.29

Nadeau-Dostie; Benoit - Gatineau CA
Nadeau-Dostie; Benoit - US
Nadeau-Dostie; Benoit - Ottawa CA
Nadeau-Dostie; Benoit - Aylmer CA
Nadeau-Dostie, Benoit - Quebec CA
Nadeau-Dostie; Benoit - Alymer CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Error-correcting code-assisted memory repair Grant 11,430,537 - Nadeau-Dostie August 30, 2	2022-08-30
Method And Apparatus For Processing Memory Repair Information App 20220215896 - Nadeau-Dostie; Benoit ; et al.	2022-07-07
Error-Correcting Code-Assisted Memory Repair App 20210174892 - Nadeau-Dostie; Benoit	2021-06-10
Test generator for low power built-in self-test Grant 8,683,280 - Rajski , et al. March 25, 2	2014-03-25
Methods for at-speed testing of memory interface Grant 8,516,317 - Nadeau-Dostie , et al. August 20, 2	2013-08-20
Test Generator For Low Power Built-In Self-Test App 20120272110 - Rajski; Janusz ; et al.	2012-10-25
Methods For At-Speed Testing Of Memory Interface App 20120198294 - Nadeau-Dostie; Benoit ; et al.	2012-08-02
Method and apparatus for storing and distributing memory repair information Grant 7,757,135 - Nadeau-Dostie , et al. July 13, 2	2010-07-13
Method For At-speed Testing Of Memory Interface Using Scan App 20100037109 - NADEAU-DOSTIE; Benoit ; et al.	2010-02-11
Method for at-speed testing of memory interface using scan Grant 7,617,425 - Nadeau-Dostie , et al. November 10, 2	2009-11-10
Clocking methodology for at-speed testing of scan circuits with synchronous clocks Grant 7,424,656 - Nadeau-Dostie , et al. September 9, 2	2008-09-09
Method and circuit for collecting memory failure information Grant 7,370,251 - Nadeau-Dostie , et al. May 6, 2	2008-05-06
Method And Apparatus For Storing And Distributing Memory Repair Information App 20080065929 - NADEAU-DOSTIE; Benoit ; et al.	2008-03-13
Method for at-speed testing of memory interface using scan App 20070266278 - Nadeau-Dostie; Benoit ; et al.	2007-11-15
Memory repair circuit and method Grant 7,257,733 - Nadeau-Dostie , et al. August 14, 2	2007-08-14
Boundary scan with strobed pad driver enable Grant 7,219,282 - Sunter , et al. May 15, 2	2007-05-15
Method and circuit for at-speed testing of scan circuits Grant 7,194,669 - Nadeau-Dostie March 20, 2	2007-03-20
Method of and program product for performing gate-level diagnosis of failing vectors Grant 7,191,374 - Maamari , et al. March 13, 2	2007-03-13
Memory repair analysis method and circuit Grant 7,188,274 - Nadeau-Dostie , et al. March 6, 2	2007-03-06
Clock controller for at-speed testing of scan circuits Grant 7,155,651 - Nadeau-Dostie , et al. December 26, 2	2006-12-26
Method and test circuit for testing memory internal write enable Grant 7,139,946 - Nadeau-Dostie , et al. November 21, 2	2006-11-21
Insertion of embedded test in RTL to GDSII flow App 20050273683 - Cote, Jean-Francois ; et al.	2005-12-08
Clocking methodology for at-speed testing of scan circuits with synchronous clocks App 20050240790 - Nadeau-Dostie, Benoit ; et al.	2005-10-27
Masking circuit and method of masking corrupted bits App 20050240848 - Cote, Jean-Francois ; et al.	2005-10-27
Clock controller for at-speed testing of scan circuits App 20050240847 - Nadeau-Dostie, Benoit ; et al.	2005-10-27
Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby Grant 6,868,532 - Nadeau-Dostie , et al. March 15, 2	2005-03-15
Method and circuit for collecting memory failure information App 20050047229 - Nadeau-Dostie, Benoit ; et al.	2005-03-03
Method and program product for designing hierarchical circuit for quiescent current testing Grant 6,862,717 - Nadeau-Dostie , et al. March 1, 2	2005-03-01
Processor interface for test access port App 20050028059 - Cote, Jean-Francois ; et al.	2005-02-03
Memory repair circuit and method App 20040257901 - Nadeau-Dostie, Benoit ; et al.	2004-12-23
Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same Grant 6,829,730 - Nadeau-Dostie , et al. December 7, 2	2004-12-07
Memory repair analysis method and circuit App 20040163015 - Nadeau-Dostie, Benoit ; et al.	2004-08-19
Method and circuit for at-speed testing of scan circuits App 20040163021 - Nadeau-Dostie, Benoit	2004-08-19
Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description Grant 6,763,489 - Nadeau-Dostie , et al. July 13, 2	2004-07-13
Test access circuit and method of accessing embedded test controllers in integrated circuit modules Grant 6,760,874 - Cote , et al. July 6, 2	2004-07-06
Method and test circuit for testing memory internal write enable App 20040123203 - Nadeau-Dostie, Benoit ; et al.	2004-06-24
Method of masking corrupt bits during signature analysis and circuit for use therewith Grant 6,745,359 - Nadeau-Dostie June 1, 2	2004-06-01
Boundary scan with strobed pad driver enable App 20040098648 - Sunter, Stephen K. ; et al.	2004-05-20
Method for collecting failure information for a memory using an embedded test controller Grant 6,738,938 - Nadeau-Dostie , et al. May 18, 2	2004-05-18
Scan Test Method For Providing Real Time Identification Of Failing Test Patterns And Test Bist Controller For Use Therewith App 20040003329 - Cote, Jean-Francois ; et al.	2004-01-01
Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith Grant 6,671,839 - Cote , et al. December 30, 2	2003-12-30
Method of masking corrupt bits during signature analysis and circuit for use therewith App 20030229833 - Nadeau-Dostie, Benoit	2003-12-11
Method for collecting failure information for a memory using an embedded test controller App 20030226073 - Nadeau-Dostie, Benoit ; et al.	2003-12-04
Method of and program product for performing gate-level diagnosis of failing vectors App 20030217315 - Maamari, Fadi ; et al.	2003-11-20
Test access circuit and method of accessing embedded test controllers in integrated circuit modules App 20030212524 - Cote, Jean-Francois ; et al.	2003-11-13
Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby Grant 6,615,392 - Nadeau-Dostie , et al. September 2, 2	2003-09-02
Method and circuitry for controlling clocks of embedded blocks during logic bist test mode Grant 6,614,263 - Nadeau-Dostie , et al. September 2, 2	2003-09-02
Method And Circuitry For Controlling Clocks Of Embedded Blocks During Logic Bist Test Mode App 20030146777 - Nadeau-Dostie, Benoit ; et al.	2003-08-07
Method and program product for designing hierarchical circuit for quiescent current testing App 20030115522 - Nadeau-Dostie, Benoit ; et al.	2003-06-19
Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby App 20030110457 - Nadeau-Dostie, Benoit ; et al.	2003-06-12
Fault insertion method, boundary scan cells, and integrated circuit for use therewith Grant 6,536,008 - Nadeau-Dostie , et al. March 18, 2	2003-03-18
Method and apparatus for testing high performance circuits Grant 6,510,534 - Nadeau-Dostie , et al. January 21, 2	2003-01-21
Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same App 20020184562 - Nadeau-Dostie, Benoit ; et al.	2002-12-05
Method for testing circuits with tri-state drivers and circuit for use therewith Grant 6,487,688 - Nadeau-Dostie November 26, 2	2002-11-26
Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description App 20020147951 - Nadeau-Dostie, Benoit ; et al.	2002-10-10
Method And Program Product For Modeling Circuits With Latch Based Design App 20020143515 - Nadeau-Dostie, Benoit ; et al.	2002-10-03
Method and program product for modeling circuits with latch based design Grant 6,457,161 - Nadeau-Dostie , et al. September 24, 2	2002-09-24
Method and apparatus for testing circuits with multiple clocks Grant 6,442,722 - Nadeau-Dostie , et al. August 27, 2	2002-08-27
Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification Grant 6,363,520 - Boubezari , et al. March 26, 2	2002-03-26
Method and apparatus for controlling power level during BIST Grant 6,330,681 - Cote , et al. December 11, 2	2001-12-11
Method of testing at-speed circuits having asynchronous clocks and controller for use therewith Grant 6,327,684 - Nadeau-Dostie , et al. December 4, 2	2001-12-04
Method and apparatus for high-speed interconnect testing Grant 6,000,051 - Nadeau-Dostie , et al. December 7, 1	1999-12-07
Asynchronous interface Grant 5,900,753 - May 4, 1	1999-05-04
Method and apparatus for testing multi-port memory Grant 5,812,469 - Nadeau-Dostie , et al. September 22, 1	1998-09-22
Multiple clock rate test apparatus for testing digital systems Grant 5,349,587 - Nadeau-Dostie , et al. September 20, 1	1994-09-20
Scan cell for weighted random pattern generation and method for its operation Grant 5,323,400 - Agarwal , et al. June 21, 1	1994-06-21
Integrated circuit testing method and apparatus and integrated circuit devices for use therewith Grant 4,996,691 - Wilcox , et al. February 26, 1	1991-02-26
Serial testing technique for embedded memories Grant 4,969,148 - Nadeau-Dostie , et al. November 6, 1	1990-11-06

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