Muzzy; Christopher David
Patent Applications and Registrations
Patent applications and USPTO patent grants for Muzzy; Christopher David.The latest application filed is for "method of changing reflectance or resistance of a region in an optoelectronic memory device".
Company Profile
0.25.24
- Muzzy; Christopher David - Burlington VT US
Patent Activity
| Patent | Date |
|---|---|
| Wafer edge conditioning for thinned wafers Grant 9,105,465 - Daubenspeck , et al. August 11, 2 | 2015-08-11 |
| Method of changing reflectance or resistance of a region in an optoelectronic memory device Grant 8,945,955 - Chen , et al. February 3, 2 | 2015-02-03 |
| Method for forming a current distribution structure Grant 8,819,933 - Daubenspeck , et al. September 2, 2 | 2014-09-02 |
| Selective electromigration improvement for high current C4s Grant 8,575,007 - Daubenspeck , et al. November 5, 2 | 2013-11-05 |
| Method Of Changing Reflectance Or Resistance Of A Region In An Optoelectronic Memory Device App 20130258765 - Chen; Fen ; et al. | 2013-10-03 |
| Substrate anchor structure and method Grant 8,361,598 - Daubenspeck , et al. January 29, 2 | 2013-01-29 |
| Optoelectronic Memory Devices App 20120287707 - Chen; Fen ; et al. | 2012-11-15 |
| Optoelectronic memory devices Grant 8,288,747 - Chen , et al. October 16, 2 | 2012-10-16 |
| Selective Electromigration Improvement For High Current C4s App 20120248604 - Daubenspeck; Timothy Harrison ; et al. | 2012-10-04 |
| Wafer Edge Conditioning For Thinned Wafers App 20120241916 - Daubenspeck; Timothy Harrison ; et al. | 2012-09-27 |
| Gap capacitors for monitoring stress in solder balls in flip chip technology Grant 7,939,390 - Ayotte , et al. May 10, 2 | 2011-05-10 |
| Substrate Anchor Structure And Method App 20110100685 - Daubenspeck; Timothy Harrison ; et al. | 2011-05-05 |
| Substrate anchor structure and method Grant 7,935,408 - Daubenspeck , et al. May 3, 2 | 2011-05-03 |
| Method For Forming A Current Distribution Structure App 20110072656 - Daubenspeck; Timothy Harrison ; et al. | 2011-03-31 |
| Current distribution structure and method Grant 7,911,803 - Daubenspeck , et al. March 22, 2 | 2011-03-22 |
| Semiconductor chips with reduced stress from underfill at edge of chip Grant 7,871,920 - Daubenspeck , et al. January 18, 2 | 2011-01-18 |
| Dual-sided chip attached modules Grant 7,863,734 - Bernstein , et al. January 4, 2 | 2011-01-04 |
| Method for forming an electrical structure comprising multiple photosensitive materials Grant 7,862,987 - Daubenspeck , et al. January 4, 2 | 2011-01-04 |
| Final via structures for bond pad-solder ball interconnections Grant 7,859,122 - Daubenspeck , et al. December 28, 2 | 2010-12-28 |
| Optoelectronic Memory Devices App 20100290264 - Chen; Fen ; et al. | 2010-11-18 |
| Semiconductor chips with reduced stress from underfill at edge of chip Grant 7,777,339 - Daubenspeck , et al. August 17, 2 | 2010-08-17 |
| Semiconductor Chips With Reduced Stress From Underfill At Edge Of Chip App 20100203685 - Daubenspeck; Timothy Harrison ; et al. | 2010-08-12 |
| Gap Capacitors For Monitoring Stress In Solder Balls In Flip Chip Technology App 20100203655 - Ayotte; Stephen P. ; et al. | 2010-08-12 |
| Gap capacitors for monitoring stress in solder balls in flip chip technology Grant 7,709,876 - Ayotte , et al. May 4, 2 | 2010-05-04 |
| Final Via Structures For Bond Pad-solder Ball Interconnections App 20090256257 - Daubenspeck; Timothy Harrison ; et al. | 2009-10-15 |
| Gap Capacitors For Monitoring Stress In Solder Balls In Flip Chip Technology App 20090201626 - Ayotte; Stephen P. ; et al. | 2009-08-13 |
| Solder wall structure in flip-chip technologies Grant 7,547,576 - Daubenspeck , et al. June 16, 2 | 2009-06-16 |
| Method For Forming An Electrical Structure Comprising Multiple Photosensitive Materials App 20090130599 - Daubenspeck; Timothy Harrison ; et al. | 2009-05-21 |
| Substrate Anchor Structure And Method App 20090110881 - Daubenspeck; Timothy H. ; et al. | 2009-04-30 |
| Current Distribution Structure And Method App 20090095519 - Daubenspeck; Timothy Harrison ; et al. | 2009-04-16 |
| Dual-sided Chip Attached Modules App 20090065925 - Bernstein; Kerry ; et al. | 2009-03-12 |
| Semiconductor Chips With Reduced Stress From Underfill At Edge Of Chip App 20090032929 - Daubenspeck; Timothy Harrison ; et al. | 2009-02-05 |
| Probing pads in kerf area for wafer testing Grant 7,482,675 - Adkisson , et al. January 27, 2 | 2009-01-27 |
| Dual-sided chip attached modules Grant 7,462,509 - Bernstein , et al. December 9, 2 | 2008-12-09 |
| Electrical interconnection structure formation Grant 7,459,785 - Daubenspeck , et al. December 2, 2 | 2008-12-02 |
| Post bump passivation for soft error protection Grant 7,348,210 - Daubenspeck , et al. March 25, 2 | 2008-03-25 |
| Electrical Interconnection Structure Formation App 20080067676 - Daubenspeck; Timothy Harrison ; et al. | 2008-03-20 |
| Dual-sided Chip Attached Modules App 20070267746 - Bernstein; Kerry ; et al. | 2007-11-22 |
| Chip Underfill In Flip-chip Technologies App 20070200229 - Daubenspeck; Timothy Harrison ; et al. | 2007-08-30 |
| Chip underfill in flip-chip technologies Grant 7,256,503 - Daubenspeck , et al. August 14, 2 | 2007-08-14 |
| Solder Wall Structure In Flip-chip Technologies App 20070176288 - Daubenspeck; Timothy H. ; et al. | 2007-08-02 |
| Electrical Interconnection Structure Formation App 20070105359 - Daubenspeck; Timothy Harrison ; et al. | 2007-05-10 |
| Probing Pads In Kerf Area For Wafer Testing App 20070013071 - Adkisson; James William ; et al. | 2007-01-18 |
| Post Bump Passivation For Soft Error Protection App 20060246703 - Daubenspeck; Timothy Harrison ; et al. | 2006-11-02 |
| Resist sidewall spacer for C4 BLM undercut control App 20060076677 - Daubenspeck; Timothy Harrison ; et al. | 2006-04-13 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 