Muth; William A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Muth; William A..The latest application filed is for "predicting wafer failure using learned probability".

Company Profile

0.7.5

Muth; William A. - Lagrangeville NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Predicting wafer failure using learned probability Grant 7,962,302 - Baseman , et al. June 14, 2	2011-06-14
Methods for normalizing error in photolithographic processes Grant 7,957,826 - Ausschnitt , et al. June 7, 2	2011-06-07
Method to control semiconductor device overlay using post etch image metrology Grant 7,879,515 - Ausschnitt , et al. February 1, 2	2011-02-01
Predicting Wafer Failure Using Learned Probability App 20100145646 - Baseman; Robert Jeffrey ; et al.	2010-06-10
Method To Control Semiconductor Device Overlay Using Post Etch Image Metrology App 20090186286 - Ausschnitt; Christopher P. ; et al.	2009-07-23
Methods And Systems For Normalizing Error App 20090053627 - Ausschnitt; Christopher P. ; et al.	2009-02-26
Method for determining semiconductor overlay on groundrule devices Grant 6,975,398 - Ausschnitt , et al. December 13, 2	2005-12-13
Combined layer-to-layer and within-layer overlay control system Grant 6,638,671 - Ausschnitt , et al. October 28, 2	2003-10-28
Combined layer-to-layer and within-layer overlay control system App 20030077527 - Ausschnitt, Christopher P. ; et al.	2003-04-24
Method for determining semiconductor overlay on groundrule devices App 20030071997 - Ausschnitt, Christopher P. ; et al.	2003-04-17
Method of measuring bias and edge overlay error for sub-0.5 micron ground rules Grant 5,757,507 - Ausschnitt , et al. May 26, 1	1998-05-26
Edge overlay measurement target for sub-0.5 micron ground rules Grant 5,712,707 - Ausschnitt , et al. January 27, 1	1998-01-27

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