Murgai; Rajeev

Patent Applications and Registrations

Patent applications and USPTO patent grants for Murgai; Rajeev.The latest application filed is for "propagating physical design information through logical design hierarchy of an electronic circuit".

Company Profile

0.10.12

Murgai; Rajeev - Bangalore IN
Murgai; Rajeev - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Propagating Physical Design Information Through Logical Design Hierarchy of an Electronic Circuit App 20220300687 - Jalota; Amit ; et al.	2022-09-22
Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree Grant 7,890,904 - Murgai , et al. February 15, 2	2011-02-15
Analyzing timing uncertainty in mesh-based architectures Grant 7,801,718 - Reddy , et al. September 21, 2	2010-09-21
System and method for providing an improved sliding window scheme for clock mesh analysis Grant 7,802,215 - Reddy , et al. September 21, 2	2010-09-21
Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture Grant 7,788,613 - Walker , et al. August 31, 2	2010-08-31
Sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture Grant 7,725,852 - Chen , et al. May 25, 2	2010-05-25
Constructing a Replica-Based Clock Tree App 20100049481 - Walker; William W. ; et al.	2010-02-25
Crosstalk-aware timing analysis Grant 7,383,522 - Murgai , et al. June 3, 2	2008-06-03
Computing current in a digital circuit based on an accurate current model for library cells Grant 7,313,771 - Reddy , et al. December 25, 2	2007-12-25
System and Method for Providing an Improved Sliding Window Scheme for Clock Mesh Analysis App 20070283305 - Reddy; Subodh M. ; et al.	2007-12-06
Analyzing Timing Uncertainty in Mesh-Based Architectures App 20070208552 - Reddy; Subodh M. ; et al.	2007-09-06
Analyzing substrate noise Grant 7,246,335 - Murgai , et al. July 17, 2	2007-07-17
Layout-driven, area-constrained design optimization Grant 7,197,732 - Murgai March 27, 2	2007-03-27
Border-Enhanced Sliding Window Scheme (SWS) for Determining Clock Timing in a Mesh-Based Clock Architecture App 20070038430 - Walker; William W. ; et al.	2007-02-15
Sliding Window Scheme (SWS) for Determining Clock Timing in a Mesh-Based Clock Architecture App 20070016882 - Chen; Hongyu ; et al.	2007-01-18
Estimating Jitter In A Clock Tree Of A Circuit And Synthesizing A Jitter-Aware And Skew-Aware Clock Tree App 20060288320 - Murgai; Rajeev ; et al.	2006-12-21
Computing current in a digital circuit based on an accurate current model for library cells App 20060225009 - Reddy; Subodh M. ; et al.	2006-10-05
Analyzing substrate noise App 20060184904 - Murgai; Rajeev ; et al.	2006-08-17
Layout-driven, area-constrained design optimization App 20060129960 - Murgai; Rajeev	2006-06-15
Crosstalk-aware timing analysis App 20060080627 - Murgai; Rajeev ; et al.	2006-04-13
Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process Grant 7,003,738 - Bhattacharya , et al. February 21, 2	2006-02-21
Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS App 20020053063 - Bhattacharya, Debashis ; et al.	2002-05-02

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