Murakata; Masami

Patent Applications and Registrations

Patent applications and USPTO patent grants for Murakata; Masami.The latest application filed is for "noise suppression circuit, asic, navigation apparatus, communication circuit, and communication apparatus having the same".

Company Profile

0.11.6

Murakata; Masami - Tokyo JP
Murakata; Masami - Kanagawa-ken JP
Murakata; Masami - Kawasaki JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same Grant 7,230,554 - Takeuchi , et al. June 12, 2	2007-06-12
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same App 20060197695 - Takeuchi; Hideki ; et al.	2006-09-07
Method for distributing clock signals to flip-flop circuits Grant 7,075,336 - Kojima , et al. July 11, 2	2006-07-11
Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same Grant 7,064,691 - Takeuchi , et al. June 20, 2	2006-06-20
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program Grant 6,813,756 - Igarashi , et al. November 2, 2	2004-11-02
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method Grant 6,645,842 - Igarashi , et al. November 11, 2	2003-11-11
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program App 20030079194 - Igarashi, Mutsunori ; et al.	2003-04-24
Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program Grant 6,546,540 - Igarashi , et al. April 8, 2	2003-04-08
Method for distributing clock signals to flip-flop circuits App 20030014724 - Kojima, Naohito ; et al.	2003-01-16
Noise suppression circuit, asic, navigation apparatus, communication circuit, and communication apparatus having the same App 20030011500 - Takeuchi, Hideki ; et al.	2003-01-16
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method App 20020182844 - Igarashi, Mutsunori ; et al.	2002-12-05
Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same Grant 6,459,331 - Takeuchi , et al. October 1, 2	2002-10-01
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method Grant 6,436,804 - Igarashi , et al. August 20, 2	2002-08-20
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method App 20010011776 - Igarashi, Mutsunori ; et al.	2001-08-09
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method Grant 6,262,487 - Igarashi , et al. July 17, 2	2001-07-17
Automatic placement method for arranging logic cells Grant 5,140,402 - Murakata August 18, 1	1992-08-18
Automatic cell-layout arranging method and apparatus for polycell logic LSI Grant 4,839,821 - Murakata June 13, 1	1989-06-13

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