Muradali; Fidel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Muradali; Fidel.The latest application filed is for "adaptive test time reduction for wafer-level testing".

Company Profile

0.8.8

Muradali; Fidel - Mountain View CA
Muradali, Fidel - Mountian View CA
Muradali; Fidel - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Adaptive test time reduction for wafer-level testing Grant 7,863,923 - Muradali January 4, 2	2011-01-04
Adaptive Test Time Reduction For Wafer-level Testing App 20100052725 - Muradali; Fidel	2010-03-04
Adaptive test time reduction for wafer-level testing Grant 7,626,412 - Muradali December 1, 2	2009-12-01
Adaptive test time reduction for wafer-level testing App 20090058451 - Muradali; Fidel	2009-03-05
Scan-test structure having increased effectiveness and related systems and methods App 20050278593 - Muradali, Fidel ; et al.	2005-12-15
Technique for debugging an integrated circuit having a parallel scan-chain architecture Grant 6,941,498 - Hartano , et al. September 6, 2	2005-09-06
Functional test design for testability (DFT) and test architecture for decreased tester channel resources App 20050138500 - Sul, Chimsong ; et al.	2005-06-23
Concurrent I/O App 20050114733 - Sul, Chimsong ; et al.	2005-05-26
Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits Grant 6,751,768 - Muradali , et al. June 15, 2	2004-06-15
Monitor circuitry and method for testing analog and/or mixed signal integrated circuits Grant 6,714,036 - Figueras , et al. March 30, 2	2004-03-30
Monitor Circuitry And Method For Testing Analog And/or Mixed Signal Integrated Circuits App 20040008049 - Figueras, Joan ; et al.	2004-01-15
Technique for debugging an integrated circuit having a parallel scan-chain architecture App 20030172334 - Hartano, Ismed D.S. ; et al.	2003-09-11
Integrated circuit with scan test structure Grant 6,587,981 - Muradali , et al. July 1, 2	2003-07-01
Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits App 20030101398 - Muradali, Fidel ; et al.	2003-05-29
Modular embedded test system for use in integrated circuits Grant 6,191,603 - Muradali , et al. February 20, 2	2001-02-20
Scan cell for weighted random pattern generation and method for its operation Grant 5,323,400 - Agarwal , et al. June 21, 1	1994-06-21

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