| Patent | Date |
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Convergence centric coverage for clock domain crossing (CDC) jitter in simulation
Grant 11,403,450 - Malani , et al. August 2, 2 | 2022-08-02 |
Automated root-cause analysis, visualization, and debugging of static verification results
Grant 11,288,427 - Bhowmick , et al. March 29, 2 | 2022-03-29 |
Reset Domain Crossing Detection And Simulation
App 20220092244 - RAHIM; Fahim ; et al. | 2022-03-24 |
State table complexity reduction in a hierarchical verification flow
Grant 11,222,154 - De , et al. January 11, 2 | 2022-01-11 |
Convergence Centric Coverage For Clock Domain Crossing (cdc) Jitter In Simulation
App 20210209279 - MALANI; Anshu ; et al. | 2021-07-08 |
State Table Complexity Reduction In A Hierarchical Verification Flow
App 20210110093 - DE; Kaushik ; et al. | 2021-04-15 |
Automated coverage convergence by correlating random variables with coverage variables sampled from simulation result data
Grant 10,831,961 - Dutta , et al. November 10, 2 | 2020-11-10 |
Automated Root-Cause Analysis, Visualization, and Debugging of Static Verification Results
App 20200349311 - BHOWMICK; Sauresh ; et al. | 2020-11-05 |
Automatic Root Cause Analysis of Complex Static Violations by Static Information Repository Exploration
App 20200174871 - Daga; Aditya ; et al. | 2020-06-04 |
Automated root-cause analysis, visualization, and debugging of static verification results
Grant 10,586,001 - Bhowmick , et al. | 2020-03-10 |
Automated Coverage Convergence By Correlating Random Variables With Coverage Variables Sampled From Simulation Result Data
App 20200019664 - Dutta; Esha ; et al. | 2020-01-16 |
System and method for generating reduced standard delay format files for gate level simulation
Grant 10,460,059 - Khandelwal , et al. Oc | 2019-10-29 |
Automated Root-Cause Analysis, Visualization, and Debugging of Static Verification Results
App 20190213288 - BHOWMICK; Sauresh ; et al. | 2019-07-11 |
Verification of circuit structures including sub-structure variants
Grant 9,886,753 - Narwade , et al. February 6, 2 | 2018-02-06 |
Accurate glitch detection
Grant 9,792,394 - De , et al. October 17, 2 | 2017-10-17 |
Accurate Glitch Detection
App 20170053051 - De; Kaushik ; et al. | 2017-02-23 |
Minimizing crossover paths for functional verification of a circuit description
Grant 9,529,948 - De , et al. December 27, 2 | 2016-12-27 |
Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit Description
App 20160180012 - Senapati; Dipti Ranjan ; et al. | 2016-06-23 |
Identifying inconsistent constraints
Grant 9,069,699 - Goswami , et al. June 30, 2 | 2015-06-30 |
Verification Of Circuit Structures Including Sub-structure Variants
App 20150131894 - Narwade; Mahantesh ; et al. | 2015-05-14 |
Ranking verification results for root cause analysis
Grant 9,032,339 - De , et al. May 12, 2 | 2015-05-12 |
Functional Verification of a Circuit Description
App 20150121326 - De; Kaushik ; et al. | 2015-04-30 |
Ranking Verification Results For Root Cause Analysis
App 20140258954 - De; Kaushik ; et al. | 2014-09-11 |
Method And Apparatus For Identifying Inconsistent Constraints
App 20120253754 - Goswami; Dhiraj ; et al. | 2012-10-04 |
Method and system for design verification and debugging of a complex computing system
Grant 7,383,168 - Mukherjee , et al. June 3, 2 | 2008-06-03 |
System, method and computer program product for equivalence checking between designs with sequential differences
Grant 7,350,168 - Mathur , et al. March 25, 2 | 2008-03-25 |
Scheduling events in a boolean satisfiability (SAT) solver
Grant 7,194,710 - Prasad , et al. March 20, 2 | 2007-03-20 |
Performing latch mapping of sequential circuits
Grant 7,032,192 - Prasad , et al. April 18, 2 | 2006-04-18 |
Scheduling events in a boolean satisfiability (SAT) solver
App 20050216871 - Prasad, Mukul R. ; et al. | 2005-09-29 |
Performing latch mapping of sequential circuits
App 20040237057 - Prasad, Mukul R. ; et al. | 2004-11-25 |
Method and system for design verification
App 20040133409 - Mukherjee, Rajarshi ; et al. | 2004-07-08 |
Multiple error and fault diagnosis based on Xlists
Grant 6,532,440 - Boppana , et al. March 11, 2 | 2003-03-11 |
Verification of sequential circuits with same state encoding
Grant 6,408,424 - Mukherjee , et al. June 18, 2 | 2002-06-18 |
Method for verification of combinational circuits using a filtering oriented approach
Grant 6,301,687 - Jain , et al. October 9, 2 | 2001-10-09 |
Method for verification of combinational circuits using a filtering oriented approach
Grant 6,086,626 - Jain , et al. July 11, 2 | 2000-07-11 |
Topology-based computer-aided design system for digital circuits and method thereof
Grant 5,649,165 - Jain , et al. July 15, 1 | 1997-07-15 |
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