Mukai; Kiyohito

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mukai; Kiyohito.The latest application filed is for "method for verification of mask layout of semiconductor integrated circuit".

Company Profile

0.9.16

Mukai; Kiyohito - Kyoto JP
Mukai; Kiyohito - Osaka JP
Mukai; Kiyohito - Souraku-gun JP
Mukai; Kiyohito - Takatsuki JP
Mukai, Kiyohito - Takatsuki-shi JP
Mukai; Kiyohito - Habikino JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor integrated circuit apparatus with low wiring resistance Grant 8,024,689 - Shinomiya , et al. September 20, 2	2011-09-20
Method For Verification Of Mask Layout Of Semiconductor Integrated Circuit App 20100242011 - Mukai; Kiyohito ; et al.	2010-09-23
Method of fabricating a semiconductor device and a method of generating a mask pattern Grant 7,707,523 - Mukai , et al. April 27, 2	2010-04-27
Reliability Design Method App 20080209367 - MUKAI; Kiyohito	2008-08-28
Semiconductor integrated circuit, and method and apparatus for designing wiring pattern of semiconductor integrated circuit App 20070272949 - Shinomiya; Noriko ; et al.	2007-11-29
Area ratio/occupancy ratio verification method and pattern generation method Grant 7,269,807 - Shimada , et al. September 11, 2	2007-09-11
Semiconductor Device Layout Inspection Method App 20070136702 - MUKAI; Kiyohito ; et al.	2007-06-14
Layout verification method and method for designing semiconductor integrated circuit device using the same Grant 7,174,527 - Itou , et al. February 6, 2	2007-02-06
Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device Grant 7,171,645 - Ito , et al. January 30, 2	2007-01-30
Method of fabricating a semiconductor device and a method of generating a mask pattern App 20070020880 - Mukai; Kiyohito ; et al.	2007-01-25
Method of fabricating a semiconductor device and a method of generating a mask pattern Grant 7,115,478 - Mukai , et al. October 3, 2	2006-10-03
Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit App 20060197573 - Matsumura; Yoichi ; et al.	2006-09-07
Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device Grant 7,062,732 - Ito , et al. June 13, 2	2006-06-13
Layout verification method and method for designing semiconductor integrated circuit device using the same App 20060115911 - Itou; Masanori ; et al.	2006-06-01
Semiconductor integrated circuit device, method of enerating pattern thereof, method of manufacturing the same, and pattern generating apparatus for the same App 20050224914 - Mukai, Kiyohito ; et al.	2005-10-13
Layout data verification method, mask pattern verification method and circuit operation verification method App 20050204327 - Mukai, Kiyohito ; et al.	2005-09-15
Area ratio/occupancy ratio verification method and pattern generation method App 20050172248 - Shimada, Junichi ; et al.	2005-08-04
Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device App 20040139412 - Ito, Mitsumi ; et al.	2004-07-15
Semiconductor device layout inspection method App 20040139407 - Mukai, Kiyohito ; et al.	2004-07-15
Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device App 20040102034 - Ito, Mitsumi ; et al.	2004-05-27
Method of fabricating a semiconductor device and a method of generating a mask pattern App 20040083445 - Mukai, Kiyohito ; et al.	2004-04-29
Method of layout compaction App 20030033581 - Mukai, Kiyohito	2003-02-13
Method of layout compaction Grant 6,473,882 - Mukai October 29, 2	2002-10-29
Method of layout compaction App 20020026621 - Mukai, Kiyohito	2002-02-28
Semiconductor device geometrical pattern correction process and geometrical pattern extraction process Grant 6,183,920 - Tsujikawa , et al. February 6, 2	2001-02-06

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