loadpatents
name:-0.036041021347046
name:-0.039844036102295
name:-0.00047206878662109
Mui; Man Patent Filings

Mui; Man

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mui; Man.The latest application filed is for "techniques for programming of select gates in nand memory".

Company Profile
0.39.31
  • Mui; Man - Fremont CA
  • Mui; Man - Santa Clara CA
  • Mui; Man - Milpitas CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Voltage generator to compensate for process corner and temperature variations
Grant 9,959,915 - Desai , et al. May 1, 2
2018-05-01
Programming techniques for non-volatile memories with charge trapping layers
Grant 9,947,395 - Louie , et al. April 17, 2
2018-04-17
Techniques for programming of select gates in NAND memory
Grant 9,947,407 - Nguyen , et al. April 17, 2
2018-04-17
Techniques For Programming Of Select Gates In NAND Memory
App 20170256317 - Nguyen; Hao ;   et al.
2017-09-07
Programming Techniques for Non-Volatile Memories with Charge Trapping Layers
App 20170221556 - Louie; Kenneth ;   et al.
2017-08-03
Voltage Generator To Compensate For Process Corner And Temperature Variations
App 20170169867 - DESAI; Amul ;   et al.
2017-06-15
Techniques for programming of select gates in NAND memory
Grant 9,659,656 - Nguyen , et al. May 23, 2
2017-05-23
Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices
Grant 9,633,742 - Desai , et al. April 25, 2
2017-04-25
Programming techniques for non-volatile memories with charge trapping layers
Grant 9,627,046 - Louie , et al. April 18, 2
2017-04-18
Utilizing NAND strings in dummy blocks for faster bit line precharge
Grant 9,595,338 - Lee , et al. March 14, 2
2017-03-14
Multi tier three-dimensional memory devices including vertically shared bit lines
Grant 9,502,471 - Lu , et al. November 22, 2
2016-11-22
Programming Techniques for Non-Volatile Memories with Charge Trapping Layers
App 20160260476 - Louie; Kenneth ;   et al.
2016-09-08
Techniques For Programming Of Select Gates In Nand Memory
App 20160189778 - NGUYEN; Hao ;   et al.
2016-06-30
Word line kick during sensing: trimming and adjacent word lines
Grant 9,318,210 - Hart , et al. April 19, 2
2016-04-19
Zoned erase verify in three dimensional nonvolatile memory
Grant 9,312,026 - Kochar , et al. April 12, 2
2016-04-12
Techniques for programming of select gates in NAND memory
Grant 9,305,648 - Nguyen , et al. April 5, 2
2016-04-05
Utilizing NAND Strings in Dummy Blocks for Faster Bit Line Precharge
App 20160086671 - Lee; Juan Carlos ;   et al.
2016-03-24
Zoned Erase Verify in Three Dimensional Nonvolatile Memory
App 20160055918 - Kochar; Mrinal ;   et al.
2016-02-25
Techniques for Programming of Select Gates in NAND Memory
App 20160055911 - Nguyen; Hao ;   et al.
2016-02-25
Back gate operation with elevated threshold voltage
Grant 9,240,238 - Raghu , et al. January 19, 2
2016-01-19
Pseudo block operation mode in 3D NAND
Grant 9,240,241 - Costa , et al. January 19, 2
2016-01-19
Segmentation of Blocks for Faster Bit Line Settling/Recovery in Non-Volatile Memory Devices
App 20160012903 - Desai; Amul Dhirajbhai ;   et al.
2016-01-14
Voltage kick to non-selected word line during programming
Grant 9,236,128 - Louie , et al. January 12, 2
2016-01-12
Optimized configurable NAND parameters
Grant 9,229,856 - Avila , et al. January 5, 2
2016-01-05
Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping
Grant 9,218,874 - Koh , et al. December 22, 2
2015-12-22
Selection of data for redundancy calculation by likely error rate
Grant 9,177,673 - Raghu , et al. November 3, 2
2015-11-03
System to reduce stress on word line select transistor during erase operation
Grant 9,142,305 - Dunga , et al. September 22, 2
2015-09-22
Bad block reconfiguration in nonvolatile memory
Grant 9,142,324 - Raghu , et al. September 22, 2
2015-09-22
Selection of data for redundancy calculation by likely error rate
Grant 9,136,022 - Raghu , et al. September 15, 2
2015-09-15
Fast-reading NAND flash memory
Grant 9,111,627 - Duzly , et al. August 18, 2
2015-08-18
Adaptive operation of three dimensional memory
Grant 9,105,349 - Avila , et al. August 11, 2
2015-08-11
Selection of data for redundancy calculation in three dimensional nonvolatile memory
Grant 9,092,363 - Avila , et al. July 28, 2
2015-07-28
Operation for non-volatile storage system with shared bit lines
Grant 9,076,544 - Mokhlesi , et al. July 7, 2
2015-07-07
Fast-reading Nand Flash Memory
App 20150170752 - Duzly; Yacov ;   et al.
2015-06-18
Systems and methods for partial page programming of multi level cells
Grant 9,058,881 - Dusija , et al. June 16, 2
2015-06-16
Systems and Methods for Partial Page Programming of Multi Level Cells
App 20150162086 - Dusija; Gautam A. ;   et al.
2015-06-11
Operation for non-volatile storage system with shared bit lines
Grant 9,047,971 - Mokhlesi , et al. June 2, 2
2015-06-02
Block Structure Profiling in Three Dimensional Memory
App 20150121156 - Raghu; Deepak ;   et al.
2015-04-30
Selection of Data for Redundancy Calculation By Likely Error Rate
App 20150117099 - Raghu; Deepak ;   et al.
2015-04-30
Selection of Data for Redundancy Calculation By Likely Error Rate
App 20150121157 - Raghu; Deepak ;   et al.
2015-04-30
Pseudo Block Operation Mode In 3D NAND
App 20150092493 - Costa; Xiying ;   et al.
2015-04-02
Back Gate Operation with Elevated Threshold Voltage
App 20150085574 - Raghu; Deepak ;   et al.
2015-03-26
Bad Block Reconfiguration in Nonvolatile Memory
App 20150063028 - Raghu; Deepak ;   et al.
2015-03-05
Select transistor tuning
Grant 8,971,119 - Avila , et al. March 3, 2
2015-03-03
Bad block reconfiguration in nonvolatile memory
Grant 8,966,330 - Raghu , et al. February 24, 2
2015-02-24
Systems and methods for partial page programming of multi level cells
Grant 8,964,467 - Dusija , et al. February 24, 2
2015-02-24
Three-dimensional NAND memory with adaptive erase
Grant 8,929,141 - Raghu , et al. January 6, 2
2015-01-06
Pseudo block operation mode in 3D NAND
Grant 8,923,054 - Costa , et al. December 30, 2
2014-12-30
Pseudo Block Operation Mode In 3d Nand
App 20140369122 - Costa; Xiying ;   et al.
2014-12-18
Pseudo Block Operation Mode In 3d Nand
App 20140369123 - Costa; Xiying ;   et al.
2014-12-18
Pseudo block operation mode in 3D NAND
Grant 8,913,431 - Costa , et al. December 16, 2
2014-12-16
Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory
App 20140359400 - Avila; Chris ;   et al.
2014-12-04
Adaptive Operation of Three Dimensional Memory
App 20140355345 - Avila; Chris ;   et al.
2014-12-04
Block structure profiling in three dimensional memory
Grant 8,902,661 - Raghu , et al. December 2, 2
2014-12-02
Three-dimensional NAND memory with adaptive erase
Grant 8,902,658 - Raghu , et al. December 2, 2
2014-12-02
Optimized Configurable NAND Parameters
App 20140351496 - Avila; Chris ;   et al.
2014-11-27
Operation For Non-volatile Storage System With Shared Bit Lines
App 20140269082 - Mokhlesi; Nima ;   et al.
2014-09-18
Select Transistor Tuning
App 20140247665 - Avila; Chris ;   et al.
2014-09-04
System To Reduce Stress On Word Line Select Transistor During Erase Operation
App 20140003150 - Dunga; Mohan Vamsi ;   et al.
2014-01-02
Operation For Non-volatile Storage System With Shared Bit Lines
App 20130128669 - Mokhlesi; Nima ;   et al.
2013-05-23
Partial speed and full speed programming for non-volatile memory using floating bit lines
Grant 8,081,514 - Mui , et al. December 20, 2
2011-12-20
Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory
Grant 7,974,134 - Zhang , et al. July 5, 2
2011-07-05
Robust sensing circuit and method
Grant 7,974,133 - Dunga , et al. July 5, 2
2011-07-05
Voltage Generator To Compensate Sense Amplifier Trip Point Over Temperature In Non-volatile Memory
App 20110116320 - Zhang; Fanglin ;   et al.
2011-05-19
Partial Speed And Full Speed Programming For Non-volatile Memory Using Floating Bit Lines
App 20110051517 - Mui; Man ;   et al.
2011-03-03
Robust Sensing Circuit And Method
App 20100172187 - Dunga; Mohan Vamsi ;   et al.
2010-07-08
Multiple bit line voltages based on distance
Grant 7,551,477 - Mokhlesi , et al. June 23, 2
2009-06-23
Multiple Bit Line Voltages Based On Distance
App 20090080265 - Mokhlesi; Nima ;   et al.
2009-03-26
Implementation of output floating scheme for hv charge pumps
Grant 7,368,979 - Govindu , et al. May 6, 2
2008-05-06
Implementation Of Output Floating Scheme For Hv Charge Pumps
App 20080068067 - Govindu; Prashanti ;   et al.
2008-03-20

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed