| Patent | Date |
|---|
System and method for controlling a memory array in an information handling system
Grant 6,412,051 - Konigsburg , et al. June 25, 2 | 2002-06-25 |
Method and system for building a multiprocessor data processing system
Grant 6,389,585 - Masleid , et al. May 14, 2 | 2002-05-14 |
Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution
Grant 6,098,167 - Cheong , et al. August 1, 2 | 2000-08-01 |
Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction
Grant 6,070,238 - Feiste , et al. May 30, 2 | 2000-05-30 |
Apparatus and method for processing multiple cache misses to a single cache line
Grant 6,021,467 - Konigsburg , et al. February 1, 2 | 2000-02-01 |
Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
Grant 6,021,485 - Feiste , et al. February 1, 2 | 2000-02-01 |
Method and apparatus for coupled phase locked loops
Grant 5,949,262 - Dreps , et al. September 7, 1 | 1999-09-07 |
Support for out-of-order execution of loads and stores in a processor
Grant 5,931,957 - Konigsburg , et al. August 3, 1 | 1999-08-03 |
Apparatus and method for instruction fetching using a multi-port instruction cache directory
Grant 5,918,044 - Levitan , et al. June 29, 1 | 1999-06-29 |
Dispatching instructions in a processor supporting out-of-order execution
Grant 5,913,048 - Cheong , et al. June 15, 1 | 1999-06-15 |
Issuing instructions in a processor supporting out-of-order execution
Grant 5,887,161 - Cheong , et al. March 23, 1 | 1999-03-23 |
Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages
Grant 5,872,950 - Levitan , et al. February 16, 1 | 1999-02-16 |
Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched
Grant 5,870,582 - Cheong , et al. February 9, 1 | 1999-02-09 |
Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding
Grant 5,864,341 - Hicks , et al. January 26, 1 | 1999-01-26 |
Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization
Grant 5,848,283 - Moore , et al. December 8, 1 | 1998-12-08 |
Cache sub-array method and apparatus for use in microprocessor integrated circuits
Grant 5,812,418 - Lattimore , et al. September 22, 1 | 1998-09-22 |
Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging
Grant 5,784,604 - Muhich , et al. July 21, 1 | 1998-07-21 |
High Speed SRAM with or-gate sense
Grant 5,729,501 - Phillips , et al. March 17, 1 | 1998-03-17 |
Method and system for achieving atomic memory references in a multilevel cache data processing system
Grant 5,706,464 - Moore , et al. January 6, 1 | 1998-01-06 |
Comparator circuit using two bit to four bit encoder
Grant 5,668,525 - Chiu , et al. September 16, 1 | 1997-09-16 |
Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length
Grant 5,640,518 - Muhich , et al. June 17, 1 | 1997-06-17 |
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