Muff; Adam J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Muff; Adam J..The latest application filed is for "superconducting circuit with virtual timing elements and related methods".

Company Profile

6.95.88

Muff; Adam J. - Woodinville WA
Muff; Adam J. - Rochester MN
Muff; Adam J. - Issaquah WA
Muff; Adam J - Rochester MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Superconducting circuit with virtual timing elements and related methods Grant 11,030,369 - Schneider , et al. June 8, 2	2021-06-08
Superconducting Circuit With Virtual Timing Elements And Related Methods App 20210064718 - Schneider; Janet L. ; et al.	2021-03-04
Instruction predication using unused datapath facilities Grant 10,776,117 - Muff , et al. Sept	2020-09-15
Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core Grant 10,521,234 - Muff , et al. Dec	2019-12-31
Instruction predication using instruction address pattern matching Grant 10,261,793 - Hickey , et al.	2019-04-16
Branch prediction with power usage prediction and control Grant 10,067,556 - Hickey , et al. September 4, 2	2018-09-04
Branch prediction with power usage prediction and control Grant 10,042,417 - Hickey , et al. August 7, 2	2018-08-07
Multi-petascale highly efficient parallel supercomputer Grant 9,971,713 - Asaad , et al. May 15, 2	2018-05-15
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Grant 9,710,274 - Muff , et al. July 18, 2	2017-07-18
Regular expression memory region with integrated regular expression engine Grant 9,678,885 - Muff , et al. June 13, 2	2017-06-13
Instruction set architecture with opcode lookup using memory attribute Grant 9,652,238 - Muff , et al. May 16, 2	2017-05-16
Instruction set architecture with opcode lookup using memory attribute Grant 9,652,239 - Muff , et al. May 16, 2	2017-05-16
Instruction set architecture with extended register addressing using one or more primary opcode bits Grant 9,632,786 - Muff , et al. April 25, 2	2017-04-25
Instruction predication using instruction filtering Grant 9,632,779 - Muff , et al. April 25, 2	2017-04-25
Indirect instruction predication Grant 9,619,234 - Muff , et al. April 11, 2	2017-04-11
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Grant 9,594,562 - Muff , et al. March 14, 2	2017-03-14
Floating point execution unit for calculating packed sum of absolute differences Grant 9,594,556 - Muff , et al. March 14, 2	2017-03-14
Floating point execution unit for calculating packed sum of absolute differences Grant 9,594,557 - Muff , et al. March 14, 2	2017-03-14
Indirect instruction predication Grant 9,582,277 - Muff , et al. February 28, 2	2017-02-28
Local instruction loop buffer utilizing execution unit register file Grant 9,542,184 - Muff , et al. January 10, 2	2017-01-10
Instruction set architecture with extensible register addressing Grant 9,507,599 - Muff , et al. November 29, 2	2016-11-29
Local instruction loop buffer utilizing execution unit register file Grant 9,501,279 - Muff , et al. November 22, 2	2016-11-22
Instruction Predication Using Unused Datapath Facilities App 20160313998 - Muff; Adam J. ; et al.	2016-10-27
Branch Prediction With Power Usage Prediction And Control App 20160313788 - Hickey; Mark J. ; et al.	2016-10-27
Instruction predication using unused datapath facilities Grant 9,465,613 - Muff , et al. October 11, 2	2016-10-11
Extensible Execution Unit Interface Architecture With Multiple Decode Logic And Multiple Execution Units App 20160224342 - Muff; Adam J. ; et al.	2016-08-04
Concurrent Multiple Instruction Issue Of Non-pipelined Instructions Using Non-pipelined Operation Resources In Another Processing Core App 20160224350 - Muff; Adam J. ; et al.	2016-08-04
Extensible Execution Unit Interface Architecture With Multiple Decode Logic And Multiple Execution Units App 20160224341 - Muff; Adam J. ; et al.	2016-08-04
Floating point execution unit for calculating packed sum of absolute differences Grant 9,405,536 - Muff , et al. August 2, 2	2016-08-02
Floating point execution unit for calculating packed sum of absolute differences Grant 9,405,535 - Muff , et al. August 2, 2	2016-08-02
Local Instruction Loop Buffer Utilizing Execution Unit Register File App 20160210148 - Muff; Adam J. ; et al.	2016-07-21
Local Instruction Loop Buffer Utilizing Execution Unit Register File App 20160210149 - Muff; Adam J. ; et al.	2016-07-21
Branch prediction with power usage prediction and control Grant 9,395,804 - Hickey , et al. July 19, 2	2016-07-19
Floating Point Execution Unit For Calculating Packed Sum Of Absolute Differences App 20160202974 - Muff; Adam J. ; et al.	2016-07-14
Indirect Instruction Predication App 20160202981 - Muff; Adam J. ; et al.	2016-07-14
Indirect Instruction Predication App 20160202982 - Muff; Adam J. ; et al.	2016-07-14
Floating Point Execution Unit For Calculating Packed Sum Of Absolute Differences App 20160202973 - Muff; Adam J. ; et al.	2016-07-14
Instruction Set Architecture With Opcode Lookup Using Memory Attribute App 20160179693 - Muff; Adam J. ; et al.	2016-06-23
Instruction Set Architecture With Opcode Lookup Using Memory Attribute App 20160179543 - Muff; Adam J. ; et al.	2016-06-23
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Grant 9,342,309 - Muff , et al. May 17, 2	2016-05-17
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Grant 9,329,870 - Muff , et al. May 3, 2	2016-05-03
Local instruction loop buffer utilizing execution unit register file Grant 9,317,291 - Muff , et al. April 19, 2	2016-04-19
Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core Grant 9,317,294 - Muff , et al. April 19, 2	2016-04-19
Local instruction loop buffer utilizing execution unit register file Grant 9,311,096 - Muff , et al. April 12, 2	2016-04-12
Indirect instruction predication Grant 9,304,771 - Muff , et al. April 5, 2	2016-04-05
Instruction set architecture with opcode lookup using memory attribute Grant 9,292,290 - Muff , et al. March 22, 2	2016-03-22
Instruction set architecture with opcode lookup using memory attribute Grant 9,286,071 - Muff , et al. March 15, 2	2016-03-15
General purpose processing unit with low power digital signal processing (DSP) mode Grant 9,274,591 - Muff , et al. March 1, 2	2016-03-01
Load latency speculation in an out-of-order computer processor Grant 9,262,160 - Heil , et al. February 16, 2	2016-02-16
Load latency speculation in an out-of-order computer processor Grant 9,256,428 - Heil , et al. February 9, 2	2016-02-09
Direct interthread communication dataport pack/unpack and load/save Grant 9,251,116 - Muff , et al. February 2, 2	2016-02-02
Multi-petascale Highly Efficient Parallel Supercomputer App 20160011996 - Asaad; Sameh ; et al.	2016-01-14
Dynamic range adjusting floating point execution unit Grant 9,223,753 - Hickey , et al. December 29, 2	2015-12-29
Branch Prediction With Power Usage Prediction And Control App 20150370308 - Hickey; Mark J. ; et al.	2015-12-24
Floating Point Execution Unit For Calculating Packed Sum Of Absolute Differences App 20150370557 - Muff; Adam J. ; et al.	2015-12-24
Instruction Set Architecture With Opcode Lookup Using Memory Attribute App 20150370566 - Muff; Adam J. ; et al.	2015-12-24
Chip level power reduction using encoded communications Grant 9,218,039 - Muff , et al. December 22, 2	2015-12-22
Processing core with speculative register preprocessing in unused execution unit cycles Grant 9,195,463 - Hickey , et al. November 24, 2	2015-11-24
Power reduction by minimizing bit transitions in the hamming distances of encoded communications Grant 9,189,051 - Muff , et al. November 17, 2	2015-11-17
Instruction set architecture with secure clear instructions for protecting processing unit architected state information Grant 9,183,399 - Muff , et al. November 10, 2	2015-11-10
Translation management instructions for updating address translation data structures in remote processing nodes Grant 9,170,954 - Muff , et al. October 27, 2	2015-10-27
Instruction set architecture with secure clear instructions for protecting processing unit architected state information Grant 9,147,078 - Muff , et al. September 29, 2	2015-09-29
Vector execution unit with prenormalization of denormal values Grant 9,092,256 - Muff , et al. July 28, 2	2015-07-28
Vector execution unit with prenormalization of denormal values Grant 9,092,257 - Muff , et al. July 28, 2	2015-07-28
Multi-petascale highly efficient parallel supercomputer Grant 9,081,501 - Asaad , et al. July 14, 2	2015-07-14
Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits Grant 9,075,599 - Hickey , et al. July 7, 2	2015-07-07
Translation management instructions for updating address translation data structures in remote processing nodes Grant 9,053,049 - Muff , et al. June 9, 2	2015-06-09
Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels Grant 9,032,191 - Muff , et al. May 12, 2	2015-05-12
Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adder Grant 8,984,260 - Muff , et al. March 17, 2	2015-03-17
Memory address translation-based data encryption with integrated encryption engine Grant 8,954,755 - Muff , et al. February 10, 2	2015-02-10
Regular Expression Memory Region With Integrated Regular Expression Engine App 20150032988 - Muff; Adam J. ; et al.	2015-01-29
Instruction Set Architecture With Opcode Lookup Using Memory Attribute App 20150032999 - Muff; Adam J. ; et al.	2015-01-29
Instruction Set Architecture With Extensible Register Addressing App 20150026435 - Muff; Adam J. ; et al.	2015-01-22
General Purpose Processing Unit With Low Power Digital Signal Processing (dsp) Mode App 20150026500 - Muff; Adam J. ; et al.	2015-01-22
System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions Grant 8,935,694 - Muff , et al. January 13, 2	2015-01-13
Floating point execution unit with fixed point functionality Grant 8,930,432 - Hickey , et al. January 6, 2	2015-01-06
Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions Grant 8,892,851 - Muff , et al. November 18, 2	2014-11-18
Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address Grant 8,880,852 - Hickey , et al. November 4, 2	2014-11-04
Instruction Set Architecture With Secure Clear Instructions For Protecting Processing Unit Architected State Information App 20140229690 - Muff; Adam J. ; et al.	2014-08-14
Local Instruction Loop Buffer Utilizing Execution Unit Register File App 20140229710 - Muff; Adam J. ; et al.	2014-08-14
Branch Prediction With Power Usage Prediction And Control App 20140229720 - Hickey; Mark J. ; et al.	2014-08-14
Indirect Instruction Predication App 20140229712 - Muff; Adam J. ; et al.	2014-08-14
Instruction Set Architecture With Secure Clear Instructions For Protecting Processing Unit Architected State Information App 20140230077 - Muff; Adam J. ; et al.	2014-08-14
Extensible Execution Unit Interface Architecture App 20140229708 - Muff; Adam J. ; et al.	2014-08-14
Indirect Instruction Predication App 20140229711 - Muff; Adam J. ; et al.	2014-08-14
Local Instruction Loop Buffer Utilizing Execution Unit Register File App 20140229714 - Muff; Adam J. ; et al.	2014-08-14
Extensible Execution Unit Interface Architecture App 20140229713 - Muff; Adam J. ; et al.	2014-08-14
Load Latency Speculation In An Out-of-order Computer Processor App 20140223143 - HEIL; TIMOTHY H. ; et al.	2014-08-07
Load Latency Speculation In An Out-Of-Order Computer Processor App 20140223144 - Heil; Timothy H. ; et al.	2014-08-07
Chip Level Power Reduction Using Encoded Communications App 20140173308 - Muff; Adam J. ; et al.	2014-06-19
Chip Level Power Reduction Using Encoded Communications App 20140173296 - Muff; Adam J. ; et al.	2014-06-19
Translation Management Instructions For Updating Address Translation Data Structures In Remote Processing Nodes App 20140164732 - Muff; Adam J. ; et al.	2014-06-12
Translation Management Instructions For Updating Address Translation Data Structures In Remote Processing Nodes App 20140164731 - Muff; Adam J. ; et al.	2014-06-12
Concurrent Multiple Instruction Issue Of Non-pipelined Instructions Using Non-pipelined Operation Resources In Another Processing Core App 20140164734 - Muff; Adam J. ; et al.	2014-06-12
Vector Execution Unit With Prenormalization Of Denormal Values App 20140164464 - Muff; Adam J. ; et al.	2014-06-12
Vector Execution Unit With Prenormalization Of Denormal Values App 20140164465 - Muff; Adam J. ; et al.	2014-06-12
Memory address translation-based data encryption/compression Grant 8,751,830 - Muff , et al. June 10, 2	2014-06-10
Floating Point Execution Unit For Calculating Packed Sum Of Absolute Differences App 20140149720 - Muff; Adam J. ; et al.	2014-05-29
Fault tolerant stability critical execution checking using redundant execution pipelines Grant 8,707,094 - Hickey , et al. April 22, 2	2014-04-22
Performing vector multiplication Grant 8,629,867 - Hickey , et al. January 14, 2	2014-01-14
Register file soft error recovery Grant 8,560,924 - Fleischer , et al. October 15, 2	2013-10-15
Instruction operand addressing using register address sequence detection Grant 8,549,262 - Mejdrich , et al. October 1, 2	2013-10-01
Programmable integrated processor blocks Grant 8,522,254 - Hickey , et al. August 27, 2	2013-08-27
Virtualization Support For Branch Prediction Logic Enable/disable App 20130191824 - Muff; Adam J. ; et al.	2013-07-25
Memory Address Translation-based Data Encryption With Integrated Encryption Engine App 20130191651 - Muff; Adam J. ; et al.	2013-07-25
Virtualization Support For Saving And Restoring Branch Prediction Logic States App 20130191825 - Muff; Adam J. ; et al.	2013-07-25
Dynamic Range Adjusting Floating Point Execution Unit App 20130191432 - Hickey; Mark J. ; et al.	2013-07-25
Memory Address Translation-based Data Encryption/compression App 20130191649 - Muff; Adam J. ; et al.	2013-07-25
Fault Tolerant Stability Critical Execution Checking Using Redundant Execution Pipelines App 20130185604 - Hickey; Mark J. ; et al.	2013-07-18
Instruction Predication Using Unused Datapath Facilities App 20130159675 - Muff; Adam J. ; et al.	2013-06-20
Instruction Predication Using Instruction Address Pattern Matching App 20130159683 - Hickey; Mark J. ; et al.	2013-06-20
Instruction Set Architecture With Extended Register Addressing App 20130159676 - Muff; Adam J. ; et al.	2013-06-20
Instruction Predication Using Instruction Filtering App 20130159674 - Muff; Adam J. ; et al.	2013-06-20
Predecode Logic For Autovectorizing Scalar Instructions In An Instruction Buffer App 20130159668 - Muff; Adam J. ; et al.	2013-06-20
Direct Interthread Communication Dataport Pack/unpack And Load/save App 20130138918 - Muff; Adam J. ; et al.	2013-05-30
Processing Core With Speculative Register Preprocessing App 20130138925 - Hickey; Mark J. ; et al.	2013-05-30
Operational Code Expansion In Response To Successive Target Address Detection App 20130111190 - Muff; Adam J. ; et al.	2013-05-02
Instruction Address Adjustment In Response To Logically Non-significant Operations App 20130111186 - Hickey; Mark J. ; et al.	2013-05-02
Dynamic range adjusting floating point execution unit Grant 8,412,760 - Hickey , et al. April 2, 2	2013-04-02
Fault tolerant stability critical execution checking using redundant execution pipelines Grant 8,412,980 - Hickey , et al. April 2, 2	2013-04-02
Floating Point Execution Unit With Fixed Point Functionality App 20130036296 - Hickey; Mark J. ; et al.	2013-02-07
Pipelined multiple operand minimum and maximum function Grant 8,356,160 - Muff , et al. January 15, 2	2013-01-15
Trigonometric summation vector execution unit Grant 8,326,904 - Muff , et al. December 4, 2	2012-12-04
Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor Grant 8,239,439 - Muff , et al. August 7, 2	2012-08-07
Opcode Space Minimizing Architecture Utilizing Instruction Address to Indicate Upper Address Bits App 20120084535 - Hickey; Mark J. ; et al.	2012-04-05
Direct inter-thread communication buffer that supports software controlled arbitrary vector operand selection in a densely threaded network on a chip Grant 8,102,884 - Muff , et al. January 24, 2	2012-01-24
Programmable Integrated Processor Blocks App 20110321049 - Hickey; Mark J. ; et al.	2011-12-29
Fault Tolerant Stability Critical Execution Checking Using Redundant Execution Pipelines App 20110302450 - Hickey; Mark J. ; et al.	2011-12-08
Performing Vector Multiplication App 20110298788 - Hickey; Mark J. ; et al.	2011-12-08
Instruction Addressing Using Register Address Sequence Detection App 20110283090 - Mejdrich; Eric O. ; et al.	2011-11-17
Data dependent instruction decode Grant 8,028,153 - Hickey , et al. September 27, 2	2011-09-27
Multi-petascale Highly Efficient Parallel Supercomputer App 20110219208 - Asaad; Sameh ; et al.	2011-09-08
Register File Soft Error Recovery App 20110167296 - Fox; Thomas W. ; et al.	2011-07-07
Redundant execution of instructions in multistage execution pipeline during unused execution cycles Grant 7,975,172 - Hickey , et al. July 5, 2	2011-07-05
Offset Based Register Address Indexing App 20110047355 - Mejdrich; Eric O. ; et al.	2011-02-24
Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip Grant 7,873,066 - Muff , et al. January 18, 2	2011-01-18
Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively Grant 7,814,303 - Muff , et al. October 12, 2	2010-10-12
Streaming Direct Inter-thread Communication Buffer Packets That Support Hardware Controlled Arbitrary Vector Operand Alignment In A Densely Threaded Network On A Chip App 20100189111 - MUFF; ADAM J. ; et al.	2010-07-29
Trigonometric Summation Vector Execution Unit App 20100191939 - Muff; Adam J. ; et al.	2010-07-29
Processing Unit With Operand Vector Multiplexer Sequence Control App 20100106940 - Muff; Adam J. ; et al.	2010-04-29
Direct Inter-thread Communication Buffer That Supports Software Controlled Arbitrary Vector Operand Selection In A Densely Threaded Network On A Chip App 20100091787 - MUFF; ADAM J. ; et al.	2010-04-15
Data Dependent Instruction Decode App 20100042812 - Hickey; Mark J. ; et al.	2010-02-18
Redundant Execution of Instructions in Multistage Execution Pipeline During Unused Execution Cycles App 20100042813 - Hickey; Mark J. ; et al.	2010-02-18
Dynamic Range Adjusting Floating Point Execution Unit App 20100023568 - Hickey; Mark J. ; et al.	2010-01-28
Method and Apparatus for a Pipelined Multiple Operand Minimum and Maximum Function App 20090182990 - Muff; Adam J. ; et al.	2009-07-16
Method and Apparatus Implementing a Minimal Area Consumption Multiple Addend Floating Point Summation Function in a Vector Microprocessor App 20090158013 - Muff; Adam J. ; et al.	2009-06-18