Muddu; Swamy

Patent Applications and Registrations

Patent applications and USPTO patent grants for Muddu; Swamy.The latest application filed is for "methods and systems for predictive analysis and/ or process control".

Company Profile

0.9.9

Muddu; Swamy - Mountain View CA
Muddu; Swamy - Milpitas CA
Muddu; Swamy - Milapitas CA
Muddu; Swamy - Sunnyvale CA US
Muddu; Swamy - La Jolla CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and systems for predictive analysis and/or process control Grant 11,397,427 - Burke , et al. July 26, 2	2022-07-26
Methods And Systems For Predictive Analysis And/ Or Process Control App 20220043439 - Burke; Timothy Matthew ; et al.	2022-02-10
Methods And Systems For Predictive Analysis And/or Process Control App 20220043440 - Burke; Timothy Matthew ; et al.	2022-02-10
Pattern-based via redundancy insertion Grant 9,189,589 - Muddu , et al. November 17, 2	2015-11-17
Pattern-based Via Redundancy Insertion App 20150169818 - Muddu; Swamy ; et al.	2015-06-18
Layout pattern correction for integrated circuits Grant 8,898,606 - Abou Ghaida , et al. November 25, 2	2014-11-25
Selection of replacement patterns for reducing manufacturing hotspots and constraint violations of IC designs Grant 8,869,077 - Ghaida , et al. October 21, 2	2014-10-21
Method and apparatus for applying post graphic data system stream enhancements Grant 8,745,553 - Muddu , et al. June 3, 2	2014-06-03
Method And Apparatus For Applying Post Graphic Data System Stream Enhancements App 20140059506 - MUDDU; Swamy ; et al.	2014-02-27
Methods for analyzing design rules Grant 8,589,844 - Muddu , et al. November 19, 2	2013-11-19
Methods For Decomposing Circuit Design Layouts And For Fabricating Semiconductor Devices Using Decomposed Patterns App 20130219347 - Zou; Yi ; et al.	2013-08-22
Methods For Analyzing Design Rules App 20130212548 - Muddu; Swamy ; et al.	2013-08-15
Method and system for wafer topography-aware integrated circuit design analysis and optimization Grant 8,024,675 - Gupta , et al. September 20, 2	2011-09-20

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