Mu; Xiao-Chun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mu; Xiao-Chun.The latest application filed is for "reliable adhesion layer interface structure for polymer memory electrode and method of making same".

Company Profile

0.22.14

Mu; Xiao-Chun - Saratogo CA
Mu; Xiao-Chun - Saratoga CA
Mu; Xiao-Chun - State College PA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reliable adhesion layer interface structure for polymer memory electrode and method of making same Grant 7,078,240 - Li , et al. July 18, 2	2006-07-18
Stepped structure for a multi-rank, stacked polymer memory device and method of making same Grant 7,018,853 - Li , et al. March 28, 2	2006-03-28
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby Grant 6,964,889 - Ma , et al. November 15, 2	2005-11-15
Stacked ferroelectric memory device and method of making same Grant 6,960,479 - Li , et al. November 1, 2	2005-11-01
Low-voltage and interface damage-free polymer memory device Grant 6,952,017 - Li , et al. October 4, 2	2005-10-04
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby Grant 6,902,950 - Ma , et al. June 7, 2	2005-06-07
Discrete polymer memory array and method of making same Grant 6,858,862 - Li , et al. February 22, 2	2005-02-22
Reliable adhesion layer interface structure for polymer memory electrode and method of making same Grant 6,798,003 - Li , et al. September 28, 2	2004-09-28
Low-voltage and interface damage-free polymer memory device App 20040150023 - Li, Jian ; et al.	2004-08-05
Reliable adhesion layer interface structure for polymer memory electrode and method of making same App 20040152231 - Li, Jian ; et al.	2004-08-05
Low-voltage and interface damage-free polymer memory device Grant 6,756,620 - Li , et al. June 29, 2	2004-06-29
Integrated core microelectronic package App 20040094830 - Vu, Quat T. ; et al.	2004-05-20
Stepped structure for a multi-rank, stacked polymer memory device and method of making same Grant 6,624,457 - Li , et al. September 23, 2	2003-09-23
Active interposer technology for high performance CMOS packaging application Grant 6,600,364 - Liang , et al. July 29, 2	2003-07-29
Process for forming microelectronic packages and intermediate structures formed therewith Grant 6,586,836 - Ma , et al. July 1, 2	2003-07-01
Reliable adhesion layer interface structure for polymer memory electrode and method of making same App 20030017623 - Li, Jian ; et al.	2003-01-23
Stacked ferroelectric memory device and method of making same App 20030017627 - Li, Jian ; et al.	2003-01-23
Stepped structure for a multi-rank, stacked polymer memory device and method of making same App 20030015740 - Li, Jian ; et al.	2003-01-23
Embedded Recess In Polymer Memory Package And Method Of Making Same App 20030017643 - Li, Jian ; et al.	2003-01-23
Discrete polymer memory array and method of making same App 20030001151 - Li, Jian ; et al.	2003-01-02
Low-voltage and interface damage-free polymer memory device App 20030001176 - Li, Jian ; et al.	2003-01-02
Process for making active interposer for high performance packaging applications Grant 6,461,895 - Liang , et al. October 8, 2	2002-10-08
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby App 20020127769 - Ma, Qing ; et al.	2002-09-12
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby App 20020127780 - Ma, Qing ; et al.	2002-09-12
Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby Grant 6,423,570 - Ma , et al. July 23, 2	2002-07-23
Flip-chip on flex for high performance packaging applications App 20020081774 - Liang, Chunlin ; et al.	2002-06-27
Microelectronic package having an integrated heat sink and build-up layers App 20020070443 - Mu, Xiao-Chun ; et al.	2002-06-13
Flip-chip on flex for high performance packaging applications Grant 6,365,962 - Liang , et al. April 2, 2	2002-04-02
Method and an apparatus for forming an under bump metallization structure App 20020028338 - Li, Jian ; et al.	2002-03-07
High density plasma physical vapor deposition Grant 5,792,522 - Jin , et al. August 11, 1	1998-08-11
Methods of forming an interconnect on a semiconductor substrate Grant 5,612,254 - Mu , et al. March 18, 1	1997-03-18
Method for the anisotropic etching of metal films in the fabrication of interconnects Grant 5,350,484 - Gardner , et al. September 27, 1	1994-09-27
Intelligent security device Grant 5,343,524 - Mu , et al. August 30, 1	1994-08-30
Novel etch back process for tungsten contact/via filling Grant 5,035,768 - Mu , et al. July 30, 1	1991-07-30
Plasma etching process for refractory metal vias Grant 4,980,018 - Mu , et al. December 25, 1	1990-12-25
Post dry-etch cleaning method for restoring wafer properties Grant 4,897,154 - Chakravarti , et al. Ja	1990-01-30

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