loadpatents
name:-0.016151905059814
name:-0.038836002349854
name:-0.0036609172821045
Moy; Dan Patent Filings

Moy; Dan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Moy; Dan.The latest application filed is for "charge trap memory devices".

Company Profile
1.36.27
  • Moy; Dan - Bethel CT
  • Moy; Dan - Hopewell Junction NY US
  • Moy; Dan - Behtel CT
  • Moy; Dan - Bethal CT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Charge trap memory devices
Grant 11,367,734 - Khan , et al. June 21, 2
2022-06-21
Charge Trap Memory Devices
App 20210242230 - KHAN; Faraz ;   et al.
2021-08-05
Back-end electrically programmable fuse
Grant 9,893,011 - Bao , et al. February 13, 2
2018-02-13
Back-end electrically programmable fuse
Grant 9,685,404 - Bao , et al. June 20, 2
2017-06-20
Rebalancing in twin cell memory schemes to enable multiple writes
Grant 9,418,745 - Chen , et al. August 16, 2
2016-08-16
E-fuse structure with methods of fusing the same and monitoring material leakage
Grant 9,337,144 - Kwon , et al. May 10, 2
2016-05-10
E-fuse structure with methods of fusing the same and monitoring material leakage
Grant 9,337,143 - Kwon , et al. May 10, 2
2016-05-10
Back-end Electrically Programmable Fuse
App 20160027733 - Bao; Junjing ;   et al.
2016-01-28
E-fuse Structure With Methods Of Fusing The Same And Monitoring Material Leakage
App 20160027734 - Kwon; O Sung ;   et al.
2016-01-28
Precision trench capacitor
Grant 9,240,406 - Feng , et al. January 19, 2
2016-01-19
Electrical fuse with bottom contacts
Grant 9,171,800 - Clevenger , et al. October 27, 2
2015-10-27
Precision Trench Capacitor
App 20150303191 - Feng; Kai D. ;   et al.
2015-10-22
Electrical Fuse With Bottom Contacts
App 20150255393 - Clevenger; Lawrence A. ;   et al.
2015-09-10
E-fuse Structure With Methods Of Fusing The Same And Monitoring Material Leakage
App 20150214149 - Moy; Dan ;   et al.
2015-07-30
Vertical electronic fuse
Grant 9,064,871 - Bao , et al. June 23, 2
2015-06-23
Fin eFuse formed by trench silicide process
Grant 9,041,151 - Lavoie , et al. May 26, 2
2015-05-26
Embedded Charge Trap Multi-time-programmable-read-only-memory For High Performance Logic Technology
App 20150138891 - Iyer; Subramanian S. ;   et al.
2015-05-21
Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology
Grant 9,025,386 - Iyer , et al. May 5, 2
2015-05-05
Fin eFuse Formed by Trench Silicide Process
App 20140353796 - Lavoie; Christian ;   et al.
2014-12-04
Vertical Electronic Fuse
App 20140332856 - Bao; Junjing ;   et al.
2014-11-13
Method of forming vertical electronic fuse interconnect structures including a conductive cap
Grant 8,841,208 - Bao , et al. September 23, 2
2014-09-23
Vertical Electronic Fuse
App 20140021578 - Bao; Junjing ;   et al.
2014-01-23
Electrically programmable fuse using anisometric contacts and fabrication method
Grant 8,629,049 - Kothandaraman , et al. January 14, 2
2014-01-14
Secure anti-fuse with low voltage programming through localized diffusion heating
Grant 8,569,755 - Li , et al. October 29, 2
2013-10-29
Electrically programmable fuse using anisometric contacts and fabrication method
Grant 8,519,507 - Kothandaraman , et al. August 27, 2
2013-08-27
Back-end Electrically Programmable Fuse
App 20130176073 - Bao; Junjing ;   et al.
2013-07-11
Apparatus and method for programming an electronically programmable semiconductor fuse
Grant 8,445,362 - Moy , et al. May 21, 2
2013-05-21
Secure Anti-fuse With Low Voltage Programming Through Localized Diffusion Heating
App 20130063202 - Li; Yan Zun ;   et al.
2013-03-14
Secure anti-fuse with low voltage programming through localized diffusion heating
Grant 8,350,264 - Li , et al. January 8, 2
2013-01-08
Electrically Programmable Fuse Using Anisometric Contacts And Fabrication Method
App 20120171857 - Kothandaraman; Chandrasekharan ;   et al.
2012-07-05
Apparatus And Method For Programming An Electronically Programmable Semiconductor Fuse
App 20120161855 - Moy; Dan ;   et al.
2012-06-28
Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor
Grant 8,159,040 - Coolbaugh , et al. April 17, 2
2012-04-17
Secure Anti-fuse With Low Voltage Programming Through Localized Diffusion Heating
App 20120012977 - Li; Yan Zun ;   et al.
2012-01-19
Metal gate compatible electrical antifuse
Grant 8,004,060 - Kim , et al. August 23, 2
2011-08-23
Electrically Programmable Fuse Using Anisometric Contacts And Fabrication Method
App 20100327399 - KOTHANDARAMAN; CHANDRASEKHARAN ;   et al.
2010-12-30
Structure of an apparatus for programming an electronically programmable semiconductor fuse
Grant 7,757,200 - Moy , et al. July 13, 2
2010-07-13
Metal Gate Integration Structure And Method Including Metal Fuse, Anti-fuse And/or Resistor
App 20090283840 - Coolbaugh; Douglas D. ;   et al.
2009-11-19
Metal Gate Compatible Electrical Antifuse
App 20090141533 - Kim; Deok-kee ;   et al.
2009-06-04
Structure Of An Apparatus For Programming An Electronically Programmable Semiconductor Fuse
App 20090128225 - Moy; Dan ;   et al.
2009-05-21
Control of buried oxide in SIMOX
Grant 7,492,008 - Fox , et al. February 17, 2
2009-02-17
Apparatus And Method For Programming An Electronically Programmable Semiconductor Fuse
App 20080089159 - Moy; Dan ;   et al.
2008-04-17
Control of buried oxide in SIMOX
App 20050003626 - Fox, Stephen Richard ;   et al.
2005-01-06
Control of buried oxide in SIMOX
Grant 6,784,072 - Fox , et al. August 31, 2
2004-08-31
T-RAM array having a planar cell structure and method for fabricating the same
Grant 6,713,791 - Hsu , et al. March 30, 2
2004-03-30
Control of buried oxide in SIMOX
App 20040013886 - Fox, Stephen Richard ;   et al.
2004-01-22
SOI hybrid structure with selective epitaxial growth of silicon
Grant 6,635,543 - Furukawa , et al. October 21, 2
2003-10-21
SOI hybrid structure with selective epitaxial growth of silicon
App 20030104658 - Furukawa, Toshiharu ;   et al.
2003-06-05
Silicon-on-insulator vertical array device trench capacitor DRAM
Grant 6,566,177 - Radens , et al. May 20, 2
2003-05-20
SOI hybrid structure with selective epitaxial growth of silicon
Grant 6,555,891 - Furukawa , et al. April 29, 2
2003-04-29
T-RAM array having a planar cell structure and method for fabricating the same
App 20020100918 - Hsu, Louis L. ;   et al.
2002-08-01
Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap
Grant 6,426,252 - Radens , et al. July 30, 2
2002-07-30
MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region
Grant 5,221,853 - Joshi , et al. June 22, 1
1993-06-22
Method for a two step selective deposition of refractory metals utilizing SiH.sub.4 reduction and H.sub.2 reduction
Grant 5,202,287 - Joshi , et al. April 13, 1
1993-04-13
Method for selective deposition of refractory metals on silicon substrates and device formed thereby
Grant 5,084,417 - Joshi , et al. January 28, 1
1992-01-28

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