Motiwala; Quaeed

Patent Applications and Registrations

Patent applications and USPTO patent grants for Motiwala; Quaeed.The latest application filed is for "multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control".

Company Profile

0.5.3

Motiwala; Quaeed - San Diego CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for efficient use of communication resources in a communication system Grant 7,590,164 - Motiwala , et al. September 15, 2	2009-09-15
Method and apparatus for processing a punctured pilot channel Grant 7,471,657 - Blessent , et al. December 30, 2	2008-12-30
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control Grant 6,615,341 - Sih , et al. September 2, 2	2003-09-02
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control App 20020138710 - Sih, Gilbert C. ; et al.	2002-09-26
Method and apparatus for efficient use of communication resources in a communication system App 20020106005 - Motiwala, Quaeed ; et al.	2002-08-08
Variable length instruction decoder Grant 6,425,070 - Zou , et al. July 23, 2	2002-07-23
Method and apparatus for processing a punctured pilot channel App 20020009064 - Blessent, Luca ; et al.	2002-01-24
Method and apparatus for processing a punctured pilot channel Grant 6,304,563 - Blessent , et al. October 16, 2	2001-10-16

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