Mosher; Dan M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mosher; Dan M..The latest application filed is for "trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom".

Company Profile

0.7.7

Mosher; Dan M. - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom Grant 7,888,196 - Sridhar , et al. February 15, 2	2011-02-15
Trench Isolation Comprising Process Having Multiple Gate Dielectric Thicknesses And Integrated Circuits Therefrom App 20100163998 - Sridhar; Seetharaman ; et al.	2010-07-01
Drain-extended MOS ESD protection structure Grant 6,804,095 - Kunz , et al. October 12, 2	2004-10-12
Drain-extended MOS ESD protection structure App 20040027745 - Kunz, Keith E. ; et al.	2004-02-12
Drain-extended MOS ESD protection structure Grant 6,624,487 - Kunz , et al. September 23, 2	2003-09-23
Method of forming a metal oxide semiconductor transistor with self-aligned channel implant Grant 6,620,692 - Scott , et al. September 16, 2	2003-09-16
Higher voltage transistors for sub micron CMOS processes App 20030127694 - Morton, Alec ; et al.	2003-07-10
Metal Oxide Semiconductor Transistor With Self-aligned Channel Implant App 20030102492 - Scott, David B. ; et al.	2003-06-05
Electrostatic discharge resistant extended drain metal oxide semiconductor transistor App 20020074606 - Mosher, Dan M.	2002-06-20
Metal oxide semiconductor transistor with self-aligned channel implant App 20020063263 - Scott, David B. ; et al.	2002-05-30
Ldmos Device With Self-aligned Resurf Region And Method Of Fabrication App 20010053581 - MOSHER, DAN M. ; et al.	2001-12-20
Resurf LDMOS device with deep drain region Grant 6,211,552 - Efland , et al. April 3, 2	2001-04-03
Complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate Grant 5,181,095 - Mosher , et al. January 19, 1	1993-01-19
Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices Grant 5,034,337 - Mosher , et al. July 23, 1	1991-07-23

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