| Patent | Date |
|---|
Interface Circuit
App 20100257324 - Osawa; Tokuya ; et al. | 2010-10-07 |
Interface circuit
Grant 7,724,606 - Osawa , et al. May 25, 2 | 2010-05-25 |
Interface circuit
App 20080031079 - Osawa; Tokuya ; et al. | 2008-02-07 |
Semiconductor integrated circuit provided with determination circuit
Grant 6,658,639 - Morooka December 2, 2 | 2003-12-02 |
Memory system having synchronous-link DRAM (SLDRAM) devices and controller
App 20030126356 - Gustavson, David B. ; et al. | 2003-07-03 |
Memory system having synchronous-link DRAM (SLDRAM) devices and controller
Grant 6,442,644 - Gustavson , et al. August 27, 2 | 2002-08-27 |
Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output
Grant 6,421,291 - Watanabe , et al. July 16, 2 | 2002-07-16 |
Circuit module
Grant 6,392,897 - Nakase , et al. May 21, 2 | 2002-05-21 |
Semiconductor Memory Device Having High Data Input/output Frequency And Capable Of Efficiently Testing Circuit Associated With Data Input/output
App 20020041532 - Watanabe, Naoya ; et al. | 2002-04-11 |
Semiconductor Integrated circuit provided with determination circuit
App 20020026623 - Morooka, Yoshikazu | 2002-02-28 |
Synchronous semiconductor memory device employing temporary data output stop scheme
Grant 6,101,151 - Watanabe , et al. August 8, 2 | 2000-08-08 |
Semiconductor memory device having controllable supplying capability of internal voltage
Grant 5,995,435 - Hamamoto , et al. November 30, 1 | 1999-11-30 |
Delay locked loop circuit
Grant 5,994,934 - Yoshimura , et al. November 30, 1 | 1999-11-30 |
Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing
Grant 5,963,502 - Watanabe , et al. October 5, 1 | 1999-10-05 |
Memory system capable of reducing timing skew between clock signal and data
Grant 5,926,837 - Watanabe , et al. July 20, 1 | 1999-07-20 |
Semiconductor memory device permitting high speed data transfer and high density integration
Grant 5,586,076 - Miyamoto , et al. December 17, 1 | 1996-12-17 |
Redundancy circuit for repairing defective bits in semiconductor memory device
Grant 5,574,729 - Kinoshita , et al. November 12, 1 | 1996-11-12 |
Semiconductor memory device providing external output data signal in accordance with states of true and complementary read buses
Grant 5,481,497 - Yamauchi , et al. January 2, 1 | 1996-01-02 |
Semiconductor memory device and method of data transfer therefor
Grant 5,481,496 - Kobayashi , et al. January 2, 1 | 1996-01-02 |
Boosting circuit improved to operate in a wider range of power supply voltage, and a semiconductor memory and a semiconductor integrated circuit device using the same
Grant 5,404,329 - Yamagata , et al. April 4, 1 | 1995-04-04 |
Semiconductor memory device comprising a test circuit and a method of operation thereof
Grant 5,384,784 - Mori , et al. January 24, 1 | 1995-01-24 |
Semiconductor integrated circuit device including a plurality of cell array blocks
Grant 5,357,478 - Kikuda , et al. October 18, 1 | 1994-10-18 |
Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit
Grant 5,323,348 - Mori , et al. June 21, 1 | 1994-06-21 |
Serial access semiconductor memory device and operating method therefor
Grant 5,200,925 - Morooka April 6, 1 | 1993-04-06 |
Semiconductor memory
Grant 4,734,889 - Mashiko , et al. March 29, 1 | 1988-03-29 |
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