Morales; Guarionex

Patent Applications and Registrations

Patent applications and USPTO patent grants for Morales; Guarionex.The latest application filed is for "methods for characterizing and reducing adverse effects of texture of semiconductor films".

Company Profile

0.12.2

Morales; Guarionex - Sunnyvale CA
MORALES, GUARIONEX - SANTA CLARA CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Surface treatment of low-K SiOF to prevent metal interaction Grant 6,444,593 - Ngo , et al. September 3, 2	2002-09-03
Method of degassing low k dielectric for metal deposition Grant 6,436,850 - Morales August 20, 2	2002-08-20
Method of reducing contact size by spacer filling Grant 6,420,104 - Rangarajan , et al. July 16, 2	2002-07-16
Methods for characterizing and reducing adverse effects of texture of semiconductor films App 20010053600 - Morales, Guarionex ; et al.	2001-12-20
Surface Treatment Of Low-k Siof To Prevent Metal Interaction App 20010044203 - HUANG, RICHARD J. ; et al.	2001-11-22
Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces Grant 6,281,584 - Ngo , et al. August 28, 2	2001-08-28
Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal Grant 6,281,121 - Brown , et al. August 28, 2	2001-08-28
Tungsten plug formation Grant 6,235,632 - Nogami , et al. May 22, 2	2001-05-22
Methods and arrangements for reducing stress and preventing cracking in a silicide layer Grant 6,211,074 - Huang , et al. April 3, 2	2001-04-03
Copper/low dielectric interconnect formation with reduced electromigration Grant 6,096,648 - Lopatin , et al. August 1, 2	2000-08-01
High density plasma oxide gap filled patterned metal layers with improved electromigration resistance Grant 6,046,106 - Tran , et al. April 4, 2	2000-04-04
Process for reducing copper oxide during integrated circuit fabrication Grant 6,033,584 - Ngo , et al. March 7, 2	2000-03-07
Vacuum baked HSQ gap fill layer for high integrity borderless vias Grant 6,030,891 - Tran , et al. February 29, 2	2000-02-29
Surface treatment of low-k SiOF to prevent metal interaction Grant 5,994,778 - Huang , et al. November 30, 1	1999-11-30

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