Mor; Yi-Shien

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mor; Yi-Shien.The latest application filed is for "method of forming a single metal that performs n work function and p work function in a high-k/metal gate process".

Company Profile

9.40.41

Mor; Yi-Shien - Hsinchu City TW
Mor; Yi-Shien - Hsinchu TW
- Hsinchu TW
Mor; Yi-Shien - Hsin-Chu TW
Mor; Yi-Shien - Taipei TW
Mor, Yi-Shien - Taipei City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method Of Forming A Single Metal That Performs N Work Function And P Work Function In A High-k/metal Gate Process App 20220216205 - Lin; Yih-Ann ; et al.	2022-07-07
Single metal that performs N work function and P work function in a high-K/metal gate Grant 11,289,481 - Lin , et al. March 29, 2	2022-03-29
Integrated Circuit Structure App 20210335785 - LEE; Yi-Juei ; et al.	2021-10-28
Method of forming semiconductor structure Grant 11,075,199 - Lee , et al. July 27, 2	2021-07-27
Fin critical dimension loading optimization Grant 11,004,747 - Liang , et al. May 11, 2	2021-05-11
Semiconductor Device And A Method For Fabricating The Same App 20200381428 - CHANG; Chih-Hao ; et al.	2020-12-03
Fin Critical Dimension Loading Optimization App 20200273754 - Liang; Chia Ming ; et al.	2020-08-27
Method for fabricating semiconductor device including contact bars having narrower portions Grant 10,748,896 - Chang , et al. A	2020-08-18
Fin critical dimension loading optimization Grant 10,692,769 - Liang , et al.	2020-06-23
Fin critical dimension loading optimization Grant 10651090 -	2020-05-12
Semiconductor device and method of forming semiconductor fin thereof Grant 10,529,862 - Liang , et al. J	2020-01-07
Semiconductor device having a contact bar over an S/D structure Grant 10,366,989 - Chang , et al. July 30, 2	2019-07-30
Method Of Forming Semiconductor Structure App 20190189614 - LEE; Yi-Juei ; et al.	2019-06-20
Fin Critical Dimension Loading Optimization App 20190067112 - Liang; Chia Ming ; et al.	2019-02-28
Semiconductor structure and manufacturing method thereof Grant 10,204,905 - Lee , et al. Feb	2019-02-12
Semiconductor Device And A Method For Fabricating The Same App 20180337177 - CHANG; Chih-Hao ; et al.	2018-11-22
Semiconductor Structure And Manufacturing Method Thereof App 20180308842 - LEE; Yi-Juei ; et al.	2018-10-25
Method of Forming a Single Metal that Performs N Work Function and P Work Function in a High-K/Metal Gate Process App 20180247937 - Lin; Yih-Ann ; et al.	2018-08-30
Semiconductor Device And Method Of Forming Semiconductor Fin Thereof App 20180151739 - Liang; Chia-Ming ; et al.	2018-05-31
Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process Grant 9,960,160 - Lin , et al. May 1, 2	2018-05-01
Semiconductor Device And A Method For Fabricating The Same App 20170229454 - CHANG; Chih-Hao ; et al.	2017-08-10
Integrated high-K/metal gate in CMOS process flow Grant 9,601,388 - Chen , et al. March 21, 2	2017-03-21
FinFETs and methods for forming the same Grant 9,466,696 - Mor , et al. October 11, 2	2016-10-11
Integrated High-K/Metal Gate in CMOS Process Flow App 20160293490 - Chen; Ryan Chia-Jen ; et al.	2016-10-06
Control fin heights in FinFET structures Grant 9,460,970 - Mor , et al. October 4, 2	2016-10-04
Integrated high-k/metal gate in CMOS process flow Grant 9,257,426 - Chen , et al. February 9, 2	2016-02-09
Control Fin Heights in FinFET Structures App 20150155208 - Mor; Yi-Shien ; et al.	2015-06-04
Control fin heights in FinFET structures Grant 8,975,698 - Mor , et al. March 10, 2	2015-03-10
Integrated High-K/Metal Gate In CMOS Process Flow App 20150061031 - Chen; Ray Chia-Jen ; et al.	2015-03-05
Method Of Making A Structure App 20150037976 - LIU; Chia-Chu ; et al.	2015-02-05
Semiconductors structure with elements having different widths and methods of making the same Grant 8,872,339 - Liu , et al. October 28, 2	2014-10-28
FinFET design with LDD extensions Grant 8,865,560 - Mor , et al. October 21, 2	2014-10-21
Integrated high-k/metal gate in CMOS process flow Grant 8,841,731 - Chen , et al. September 23, 2	2014-09-23
Control Fin Heights in FinFET Structures App 20140103453 - Mor; Yi-Shien ; et al.	2014-04-17
Control fin heights in FinFET structures Grant 8,659,097 - Mor , et al. February 25, 2	2014-02-25
Method Of Forming A Single Metal That Performs N Work Function And P Work Function In A High-K/Metal Gate Process App 20140001566 - Lin; Yih-Ann ; et al.	2014-01-02
FinFET Design with LDD Extensions App 20130228876 - Mor; Yi-Shien ; et al.	2013-09-05
Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process Grant 8,524,588 - Lin , et al. September 3, 2	2013-09-03
Structure And Method Of Making The Same App 20130207265 - LIU; Chia-Chu ; et al.	2013-08-15
FinFETs and Methods for Forming the Same App 20130187206 - Mor; Yi-Shien ; et al.	2013-07-25
Control Fin Heights in FinFET Structures App 20130181300 - Mor; Yi-Shien ; et al.	2013-07-18
Spacer shape engineering for void-free gap-filling process Grant 8,461,654 - Wu , et al. June 11, 2	2013-06-11
Integrated High-k/metal Gate In Cmos Process Flow App 20130140643 - Chen; Ryan Chia-Jen ; et al.	2013-06-06
Integrated high-K/metal gate in CMOS process flow Grant 8,383,502 - Chen , et al. February 26, 2	2013-02-26
High-k metal gate CMOS patterning method Grant 8,349,680 - Thei , et al. January 8, 2	2013-01-08
Spacer Shape Engineering for Void-Free Gap-Filling Process App 20120025329 - Wu; Ming-Yuah ; et al.	2012-02-02
Integrated High-K/Metal Gate in CMOS Process Flow App 20110275212 - Chen; Ryan Chia-Jen ; et al.	2011-11-10
Spacer shape engineering for void-free gap-filling process Grant 8,048,752 - Wu , et al. November 1, 2	2011-11-01
Method of integrating high-K/metal gate in CMOS process flow Grant 8,003,507 - Chen , et al. August 23, 2	2011-08-23
Semiconductor devices with dual-metal gate structures and fabrication methods thereof Grant 7,947,591 - Hsu , et al. May 24, 2	2011-05-24
Novel High-k Metal Gate Cmos Patterning Method App 20100048013 - Thei; Kong-Beng ; et al.	2010-02-25
Method Of Forming A Single Metal That Performs N Work Function And P Work Function In A High-k/metal Gate Process App 20100038721 - Lin; Yih-Ann ; et al.	2010-02-18
Method Of Integrating High-k/metal Gate In Cmos Process Flow App 20100041223 - Chen; Ryan Chia-Jen ; et al.	2010-02-18
Spacer Shape Engineering for Void-Free Gap-Filling Process App 20100022061 - Wu; Ming-Yuan ; et al.	2010-01-28
Semiconductor Devices With Dual-metal Gate Structures And Fabrication Methods Thereof App 20080188044 - Hsu; Peng-Fu ; et al.	2008-08-07
Method for forming silicide and semiconductor device formed thereby Grant 7,382,028 - Hsieh , et al. June 3, 2	2008-06-03
Semiconductor devices with dual-metal gate structures and fabrication methods thereof Grant 7,378,713 - Hsu , et al. May 27, 2	2008-05-27
Semiconductor Devices With Dual-metal Gate Structures And Fabrication Methods Thereof App 20080099851 - Hsu; Peng-Fu ; et al.	2008-05-01
Method for forming silicide and semiconductor device formed thereby App 20060231910 - Hsieh; Tung-Heng ; et al.	2006-10-19
Method of avoiding dielectric layer deterioation with a low dielectric constant during a stripping process Grant 6,979,654 - Chang , et al. December 27, 2	2005-12-27
Air gap semiconductor structure and method of manufacture Grant 6,635,967 - Chang , et al. October 21, 2	2003-10-21
Method of avoiding dielectric layer deterioration with a low dielectric constant Grant 6,583,067 - Chang , et al. June 24, 2	2003-06-24
Method of repairing a low dielectric constant material layer Grant 6,521,547 - Chang , et al. February 18, 2	2003-02-18
Method of avoiding dielectric layer deterioation with a low dielectric constant during a stripping process App 20030013311 - Chang, Ting-Chang ; et al.	2003-01-16
Method of avoiding dielectric layer deterioation with a low dielectric constant App 20030008518 - Chang, Ting-Chang ; et al.	2003-01-09
Method of reinforcing a low dielectric constant material layer against damage caused by a photoresist stripper App 20030008516 - Chang, Ting-Chang ; et al.	2003-01-09
Method for forming a silicon dioxide-low k dielectric stack App 20020164868 - Chang, Ting-Chang ; et al.	2002-11-07
Post-processing treatment of low dielectric constant material Grant 6,423,652 - Chang , et al. July 23, 2	2002-07-23
Air gap semiconductor structure and method of manufacture App 20020090794 - Chang, Ting-Chang ; et al.	2002-07-11
Air gap semiconductor structure and method of manufacture Grant 6,316,347 - Chang , et al. November 13, 2	2001-11-13
Air gap semiconductor structure and method of manufacture App 20010007788 - Chang, Ting-Chang ; et al.	2001-07-12