Moon; Cho
Patent Applications and Registrations
Patent applications and USPTO patent grants for Moon; Cho.The latest application filed is for "automatic reduction of modes of electronic circuits for timing analysis".
- Moon; Cho - San Diego CA
| Patent | Date |
|---|---|
| Automatic reduction of modes of electronic circuits for timing analysis Grant 8,701,074 - Sripada , et al. April 15, 2 | 2014-04-15 |
| Automatic generation of merged mode constraints for electronic circuits Grant 8,627,262 - Sripada , et al. January 7, 2 | 2014-01-07 |
| Automatic verification of merged mode constraints for electronic circuits Grant 8,607,186 - Sripada , et al. December 10, 2 | 2013-12-10 |
| Automatic Reduction Of Modes Of Electronic Circuits For Timing Analysis App 20120324410 - Sripada; Subramanyam ; et al. | 2012-12-20 |
| Comparing timing constraints of circuits Grant 8,261,221 - Singhal , et al. September 4, 2 | 2012-09-04 |
| Automatic Generation Of Merged Mode Constraints For Electronic Circuits App 20110252393 - Sripada; Subramanyam ; et al. | 2011-10-13 |
| Comparing Timing Constraints Of Circuits App 20110252388 - Singhal; Sonia ; et al. | 2011-10-13 |
| Automatic Verification Of Merged Mode Constraints For Electronic Circuits App 20110252390 - Sripada; Subramanyam ; et al. | 2011-10-13 |
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