Montoye; Robert Kevin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Montoye; Robert Kevin.The latest application filed is for "sort-merge-join on a large architected register file".

Company Profile

2.33.32

Montoye; Robert Kevin - Yorktown Heights NY US
Montoye; Robert Kevin - Rochester MN
Montoye; Robert Kevin - New York NY US
Montoye; Robert Kevin - Austin TX
Montoye; Robert Kevin - Cold Spring NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Local computation logic embedded in a register file to accelerate programs Grant 10,534,608 - Bose , et al. January 14, 2	2020-01-14
Sort-merge-join on a large architected register file Grant 10,042,876 - Derby , et al. August 7, 2	2018-08-07
Sort-merge-join On A Large Architected Register File App 20160078031 - Derby; Jeffrey H. ; et al.	2016-03-17
Methods for generating code for an architecture encoding an extended register specification Grant 8,893,095 - Gschwind , et al. November 18, 2	2014-11-18
Methods for generating code for an architecture encoding an extended register specification Grant 8,893,079 - Gschwind , et al. November 18, 2	2014-11-18
Enhanced data retention mode for dynamic memories Grant 8,605,489 - Reohr , et al. December 10, 2	2013-12-10
Enhanced Data Retention Mode for Dynamic Memories App 20130135941 - Reohr; William Robert ; et al.	2013-05-30
Local Computation Logic Embedded in a Register File to Accelerate Programs App 20130046955 - Bose; Pradip ; et al.	2013-02-21
Methods For Generating Code For An Architecture Encoding An Extended Register Specification App 20120297373 - Gschwind; Michael K. ; et al.	2012-11-22
Methods For Generating Code For An Architecture Encoding An Extended Register Specification App 20120297171 - Gschwind; Michael Karl ; et al.	2012-11-22
Methods for generating code for an architecture encoding an extended register specification Grant 8,312,424 - Gschwind , et al. November 13, 2	2012-11-13
Implementing instruction set architectures with non-contiguous register file specifiers Grant 8,166,281 - Gschwind , et al. April 24, 2	2012-04-24
Dynamic memory architecture employing passive expiration of data Grant 8,020,073 - Emma , et al. September 13, 2	2011-09-13
System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation App 20100266081 - Ditlow; Gary S. ; et al.	2010-10-21
Implementing instruction set architectures with non-contiguous register file specifiers Grant 7,793,081 - Gschwind , et al. September 7, 2	2010-09-07
Implementing Instruction Set Architectures With Non-contiguous Register File Specifiers App 20090300331 - Gschwind; Michael Karl ; et al.	2009-12-03
Dynamic Memory Architecture Employing Passive Expiration Of Data App 20090019341 - Emma; Philip George ; et al.	2009-01-15
Transient cache storage with discard function for disposable data Grant 7,461,209 - Altman , et al. December 2, 2	2008-12-02
Methods For Generating Code For An Architecture Encoding An Extended Register Specification App 20080215856 - Gschwind; Michael Karl ; et al.	2008-09-04
Implementing instruction set architectures with non-contiguous register file specifiers Grant 7,421,566 - Gschwind , et al. September 2, 2	2008-09-02
Implementing Instruction Set Architectures With Non-contiguous Register File Specifiers App 20080189519 - Gschwind; Michael Karl ; et al.	2008-08-07
Scanning Latches Using Selecting Array App 20080163019 - Martin; Andrew Kenneth ; et al.	2008-07-03
Scanning Latches Using Selecting Array App 20080144400 - Martin; Andrew Kenneth ; et al.	2008-06-19
Scanning latches using selecting array Grant 7,383,480 - Martin , et al. June 3, 2	2008-06-03
Ultra High-speed Nor-type Lsdl/domino Combined Address Decoder App 20080084777 - Montoye; Robert Kevin ; et al.	2008-04-10
Ultra high-speed Nor-type LSDL/Domino combined address decoder Grant 7,349,288 - Montoye , et al. March 25, 2	2008-03-25
Shift-and-negate unit within a fused multiply-adder circuit Grant 7,337,202 - Datta , et al. February 26, 2	2008-02-26
Dynamic memory architecture employing passive expiration of data Grant 7,290,203 - Emma , et al. October 30, 2	2007-10-30
Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock Grant 7,282,960 - Belluomini , et al. October 16, 2	2007-10-16
Transient cache storage App 20070130237 - Altman; Erik R. ; et al.	2007-06-07
Implementing instruction set architectures with non-contiguous register file specifiers App 20070038848 - Gschwind; Michael Karl ; et al.	2007-02-15
Methods for generating code for an architecture encoding an extended register specification App 20070038984 - Gschwind; Michael Karl ; et al.	2007-02-15
Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock App 20060290385 - Belluomini; Wendy Ann ; et al.	2006-12-28
Memory cell having improved read stability Grant 7,106,620 - Chang , et al. September 12, 2	2006-09-12
Memory Cell Having Improved Read Stability App 20060146638 - Chang; Leland ; et al.	2006-07-06
Dynamic memory architecture employing passive expiration of data App 20060107090 - Emma; Philip George ; et al.	2006-05-18
Method and apparatus for low overhead circuit scan Grant 7,047,468 - Belluomini , et al. May 16, 2	2006-05-16
Method and apparatus for performing bit-aligned permute Grant 7,014,122 - Datta , et al. March 21, 2	2006-03-21
Scanning latches using selecting array App 20060020863 - Martin; Andrew Kenneth ; et al.	2006-01-26
Method and apparatus for performing bit-aligned permute App 20050139647 - Datta, Ramyanshu ; et al.	2005-06-30
Shift-and-negate unit within a fused multiply-adder circuit App 20050144214 - Datta, Ramyanshu ; et al.	2005-06-30
Variable pulse width and pulse separation clock generator Grant 6,891,399 - Ngo , et al. May 10, 2	2005-05-10
Method and apparatus for low overhead circuit scan App 20050071717 - Belluomini, Wendy Ann ; et al.	2005-03-31
Variable pulse width and pulse separation clock generator App 20040178838 - Ngo, Hung Cai ; et al.	2004-09-16
Spacer-connector stud for stacked surface laminated multi-chip modules and methods of manufacture Grant 6,667,555 - Cohn , et al. December 23, 2	2003-12-23
Circuits and systems for limited switch dynamic logic Grant 6,650,145 - Ngo , et al. November 18, 2	2003-11-18
Circuits And Systems For Limited Switch Dynamic Logic App 20030189445 - Ngo, Hung Cai ; et al.	2003-10-09
Method and apparatus for improved compression and decompression Grant 6,618,506 - Auerbach , et al. September 9, 2	2003-09-09
Spacer-connector stud for stacked surface laminated multi-chip modules and methods of manufacture App 20030075811 - Cohn, David Leslie ; et al.	2003-04-24
Fast, symmetrical XOR/XNOR gate App 20030058001 - Boerstler, David William ; et al.	2003-03-27
Spacer - Connector Stud For Stacked Surface Laminated Multichip Modules And Methods Of Manufacture App 20030038373 - Cohn, David Leslie ; et al.	2003-02-27
Multi-chip integrated circuit module Grant 6,507,115 - Hofstee , et al. January 14, 2	2003-01-14
Method and system for managing innovation by encouraging reusability and subsequent reuse of design components App 20020198773 - Belluomini, Wendy Ann ; et al.	2002-12-26
Multi-chip integrated circuit module App 20020074668 - Hofstee, Harm Peter ; et al.	2002-06-20
Electronic package with interconnected chips Grant 6,326,696 - Horton , et al. December 4, 2	2001-12-04
Method of fabricating an electronic package with interconnected chips Grant 6,306,686 - Horton , et al. October 23, 2	2001-10-23
Portable computing device having a display movable thereabout Grant 6,262,885 - Emma , et al. July 17, 2	2001-07-17
Processor transparent on-the-fly instruction stream decompression Grant 6,199,126 - Auerbach , et al. March 6, 2	2001-03-06
Method and system for compressing microcode to be executed within a data processing system Grant 5,745,058 - Auerbach , et al. April 28, 1	1998-04-28