Mone; Patrick
Patent Applications and Registrations
Patent applications and USPTO patent grants for Mone; Patrick.The latest application filed is for "phase-locked loop".
- Mone; Patrick - Valbonne FR
- Mone; Patrick - Ponthierry FR
| Patent | Date |
|---|---|
| Calibratable phase-locked loop Grant 7,106,140 - Mone September 12, 2 | 2006-09-12 |
| Phase-locked loop App 20050174180 - Mone, Patrick | 2005-08-11 |
| Temperature compensated reference current generator Grant 5,783,936 - Girard , et al. July 21, 1 | 1998-07-21 |
| Highly symmetrical bi-direction current sources Grant 5,760,640 - Girard , et al. June 2, 1 | 1998-06-02 |
| Stacked conductive resistive polysilicon lands in multilevel semiconductor chips Grant 5,381,046 - Cederbaum , et al. January 10, 1 | 1995-01-10 |
| Method of forming thin film pseudo-planar FET devices and structures resulting therefrom Grant 5,320,975 - Cederbaum , et al. June 14, 1 | 1994-06-14 |
| Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom Grant 5,275,963 - Cederbaum , et al. January 4, 1 | 1994-01-04 |
| Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom Grant 5,100,817 - Cederbaum , et al. March 31, 1 | 1992-03-31 |
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